/[gxemul]/trunk/src/devices/dev_footbridge.c
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Contents of /trunk/src/devices/dev_footbridge.c

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Revision 20 - (show annotations)
Mon Oct 8 16:19:23 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 13109 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_footbridge.c,v 1.36 2005/11/21 09:17:26 debug Exp $
29 *
30 * Footbridge. Used in Netwinder and Cats.
31 *
32 * TODO:
33 * o) Add actual support for the fcom serial port.
34 * o) FIQs.
35 */
36
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <string.h>
40
41 #include "bus_pci.h"
42 #include "console.h"
43 #include "cpu.h"
44 #include "device.h"
45 #include "devices.h" /* for struct footbridge_data */
46 #include "machine.h"
47 #include "memory.h"
48 #include "misc.h"
49
50
51 #include "dc21285reg.h"
52
53 #define DEV_FOOTBRIDGE_TICK_SHIFT 14
54 #define DEV_FOOTBRIDGE_LENGTH 0x400
55 #define TIMER_POLL_THRESHOLD 15
56
57
58 /*
59 * dev_footbridge_tick():
60 *
61 * The 4 footbridge timers should decrease every now and then, and cause
62 * interrupts. Periodic interrupts restart as soon as they are acknowledged,
63 * non-periodic interrupts need to be "reloaded" to restart.
64 */
65 void dev_footbridge_tick(struct cpu *cpu, void *extra)
66 {
67 int i;
68 struct footbridge_data *d = (struct footbridge_data *) extra;
69
70 if (!d->timer_being_read)
71 d->timer_poll_mode = 0;
72
73 for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
74 int amount = 1 << DEV_FOOTBRIDGE_TICK_SHIFT;
75 if (d->timer_control[i] & TIMER_FCLK_16)
76 amount >>= 4;
77 else if (d->timer_control[i] & TIMER_FCLK_256)
78 amount >>= 8;
79
80 if (d->timer_tick_countdown[i] == 0)
81 continue;
82
83 if (d->timer_value[i] > amount)
84 d->timer_value[i] -= amount;
85 else
86 d->timer_value[i] = 0;
87
88 if (d->timer_value[i] == 0) {
89 d->timer_tick_countdown[i] --;
90 if (d->timer_tick_countdown[i] > 0)
91 continue;
92
93 if (d->timer_control[i] & TIMER_ENABLE)
94 cpu_interrupt(cpu, IRQ_TIMER_1 + i);
95 d->timer_tick_countdown[i] = 0;
96 }
97 }
98 }
99
100
101 /*
102 * dev_footbridge_isa_access():
103 *
104 * Reading the byte at 0x79000000 is a quicker way to figure out which ISA
105 * interrupt has occurred (and acknowledging it at the same time), than
106 * dealing with the legacy 0x20/0xa0 ISA ports.
107 */
108 int dev_footbridge_isa_access(struct cpu *cpu, struct memory *mem,
109 uint64_t relative_addr, unsigned char *data, size_t len,
110 int writeflag, void *extra)
111 {
112 /* struct footbridge_data *d = extra; */
113 uint64_t idata = 0, odata = 0;
114 int x;
115
116 if (writeflag == MEM_WRITE) {
117 idata = memory_readmax64(cpu, data, len);
118 fatal("[ footbridge_isa: WARNING/TODO: write! ]\n");
119 }
120
121 x = cpu->machine->isa_pic_data.last_int;
122 if (x == 0)
123 cpu_interrupt_ack(cpu, 32 + x);
124
125 if (x < 8)
126 odata = cpu->machine->isa_pic_data.pic1->irq_base + x;
127 else
128 odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8;
129
130 if (writeflag == MEM_READ)
131 memory_writemax64(cpu, data, len, odata);
132
133 return 1;
134 }
135
136
137 /*
138 * dev_footbridge_pci_access():
139 *
140 * The Footbridge PCI configuration space is not implemented as "address +
141 * data port" pair, but instead a 24-bit (16 MB) chunk of physical memory
142 * decodes as the address. This function translates that into bus_pci_access
143 * calls.
144 */
145 int dev_footbridge_pci_access(struct cpu *cpu, struct memory *mem,
146 uint64_t relative_addr, unsigned char *data, size_t len,
147 int writeflag, void *extra)
148 {
149 struct footbridge_data *d = extra;
150 uint64_t idata = 0, odata = 0;
151 int bus, device, function, regnr, res;
152 uint64_t pci_word;
153
154 if (writeflag == MEM_WRITE)
155 idata = memory_readmax64(cpu, data, len);
156
157 bus = (relative_addr >> 16) & 0xff;
158 device = (relative_addr >> 11) & 0x1f;
159 function = (relative_addr >> 8) & 0x7;
160 regnr = relative_addr & 0xff;
161
162 if (bus == 255) {
163 fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"
164 " pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc);
165 exit(1);
166 }
167
168 debug("[ footbridge_pci: %s bus %i, device %i, function "
169 "%i, register %i ]\n", writeflag == MEM_READ? "read from"
170 : "write to", bus, device, function, regnr);
171
172 if (d->pcibus == NULL) {
173 fatal("dev_footbridge_pci_access(): no PCI bus?\n");
174 return 0;
175 }
176
177 pci_word = relative_addr & 0x00ffffff;
178
179 res = bus_pci_access(cpu, mem, BUS_PCI_ADDR,
180 &pci_word, sizeof(uint32_t), MEM_WRITE, d->pcibus);
181 if (writeflag == MEM_READ) {
182 res = bus_pci_access(cpu, mem, BUS_PCI_DATA,
183 &pci_word, len, MEM_READ, d->pcibus);
184 odata = pci_word;
185 } else {
186 pci_word = idata;
187 res = bus_pci_access(cpu, mem, BUS_PCI_DATA,
188 &pci_word, len, MEM_WRITE, d->pcibus);
189 }
190
191 if (writeflag == MEM_READ)
192 memory_writemax64(cpu, data, len, odata);
193
194 return 1;
195 }
196
197
198 /*
199 * dev_footbridge_access():
200 *
201 * The DC21285 registers.
202 */
203 int dev_footbridge_access(struct cpu *cpu, struct memory *mem,
204 uint64_t relative_addr, unsigned char *data, size_t len,
205 int writeflag, void *extra)
206 {
207 struct footbridge_data *d = extra;
208 uint64_t idata = 0, odata = 0;
209 int timer_nr = 0;
210
211 if (writeflag == MEM_WRITE)
212 idata = memory_readmax64(cpu, data, len);
213
214 if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) {
215 timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1);
216 relative_addr &= ~0x060;
217 }
218
219 switch (relative_addr) {
220
221 case VENDOR_ID:
222 odata = 0x1011; /* DC21285_VENDOR_ID */
223 break;
224
225 case DEVICE_ID:
226 odata = 0x1065; /* DC21285_DEVICE_ID */
227 break;
228
229 case 0x04:
230 case 0x0c:
231 case 0x10:
232 case 0x14:
233 case 0x18:
234 /* TODO. Written to by Linux. */
235 break;
236
237 case REVISION:
238 odata = 3; /* footbridge revision number */
239 break;
240
241 case PCI_ADDRESS_EXTENSION:
242 /* TODO: Written to by Linux. */
243 if (writeflag == MEM_WRITE && idata != 0)
244 fatal("[ footbridge: TODO: write to PCI_ADDRESS_"
245 "EXTENSION: 0x%llx ]\n", (long long)idata);
246 break;
247
248 case UART_DATA:
249 if (writeflag == MEM_WRITE)
250 console_putchar(d->console_handle, idata);
251 break;
252
253 case UART_RX_STAT:
254 /* TODO */
255 odata = 0;
256 break;
257
258 case UART_FLAGS:
259 odata = UART_TX_EMPTY;
260 break;
261
262 case IRQ_STATUS:
263 if (writeflag == MEM_READ)
264 odata = d->irq_status & d->irq_enable;
265 else {
266 fatal("[ WARNING: footbridge write to irq status? ]\n");
267 exit(1);
268 }
269 break;
270
271 case IRQ_RAW_STATUS:
272 if (writeflag == MEM_READ)
273 odata = d->irq_status;
274 else {
275 fatal("[ footbridge write to irq_raw_status ]\n");
276 exit(1);
277 }
278 break;
279
280 case IRQ_ENABLE_SET:
281 if (writeflag == MEM_WRITE) {
282 d->irq_enable |= idata;
283 cpu_interrupt(cpu, 64);
284 } else {
285 odata = d->irq_enable;
286 fatal("[ WARNING: footbridge read from "
287 "ENABLE SET? ]\n");
288 exit(1);
289 }
290 break;
291
292 case IRQ_ENABLE_CLEAR:
293 if (writeflag == MEM_WRITE) {
294 d->irq_enable &= ~idata;
295 cpu_interrupt(cpu, 64);
296 } else {
297 odata = d->irq_enable;
298 fatal("[ WARNING: footbridge read from "
299 "ENABLE CLEAR? ]\n");
300 exit(1);
301 }
302 break;
303
304 case FIQ_STATUS:
305 if (writeflag == MEM_READ)
306 odata = d->fiq_status & d->fiq_enable;
307 else {
308 fatal("[ WARNING: footbridge write to fiq status? ]\n");
309 exit(1);
310 }
311 break;
312
313 case FIQ_RAW_STATUS:
314 if (writeflag == MEM_READ)
315 odata = d->fiq_status;
316 else {
317 fatal("[ footbridge write to fiq_raw_status ]\n");
318 exit(1);
319 }
320 break;
321
322 case FIQ_ENABLE_SET:
323 if (writeflag == MEM_WRITE)
324 d->fiq_enable |= idata;
325 break;
326
327 case FIQ_ENABLE_CLEAR:
328 if (writeflag == MEM_WRITE)
329 d->fiq_enable &= ~idata;
330 break;
331
332 case TIMER_1_LOAD:
333 if (writeflag == MEM_READ)
334 odata = d->timer_load[timer_nr];
335 else {
336 d->timer_value[timer_nr] =
337 d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;
338 debug("[ footbridge: timer %i (1-based), value %i ]\n",
339 timer_nr + 1, (int)d->timer_value[timer_nr]);
340 d->timer_tick_countdown[timer_nr] = 1;
341 cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);
342 }
343 break;
344
345 case TIMER_1_VALUE:
346 if (writeflag == MEM_READ) {
347 /*
348 * NOTE/TODO: This is INCORRECT but speeds up NetBSD
349 * and OpenBSD boot sequences: if the timer is polled
350 * "very often" (such as during bootup), then this
351 * causes the timers to expire quickly.
352 */
353 d->timer_being_read = 1;
354 d->timer_poll_mode ++;
355 if (d->timer_poll_mode >= TIMER_POLL_THRESHOLD) {
356 d->timer_poll_mode = TIMER_POLL_THRESHOLD;
357 dev_footbridge_tick(cpu, d);
358 dev_footbridge_tick(cpu, d);
359 dev_footbridge_tick(cpu, d);
360 }
361 odata = d->timer_value[timer_nr];
362 d->timer_being_read = 0;
363 } else
364 d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;
365 break;
366
367 case TIMER_1_CONTROL:
368 if (writeflag == MEM_READ)
369 odata = d->timer_control[timer_nr];
370 else {
371 d->timer_control[timer_nr] = idata;
372 if (idata & TIMER_FCLK_16 &&
373 idata & TIMER_FCLK_256) {
374 fatal("TODO: footbridge timer: "
375 "both 16 and 256?\n");
376 exit(1);
377 }
378 if (idata & TIMER_ENABLE) {
379 d->timer_value[timer_nr] =
380 d->timer_load[timer_nr];
381 d->timer_tick_countdown[timer_nr] = 1;
382 }
383 cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);
384 }
385 break;
386
387 case TIMER_1_CLEAR:
388 if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {
389 d->timer_value[timer_nr] = d->timer_load[timer_nr];
390 d->timer_tick_countdown[timer_nr] = 1;
391 }
392 cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);
393 break;
394
395 default:if (writeflag == MEM_READ) {
396 fatal("[ footbridge: read from 0x%x ]\n",
397 (int)relative_addr);
398 } else {
399 fatal("[ footbridge: write to 0x%x: 0x%llx ]\n",
400 (int)relative_addr, (long long)idata);
401 }
402 }
403
404 if (writeflag == MEM_READ)
405 memory_writemax64(cpu, data, len, odata);
406
407 return 1;
408 }
409
410
411 /*
412 * devinit_footbridge():
413 */
414 int devinit_footbridge(struct devinit *devinit)
415 {
416 struct footbridge_data *d;
417 uint64_t pci_addr = 0x7b000000;
418 int i;
419
420 d = malloc(sizeof(struct footbridge_data));
421 if (d == NULL) {
422 fprintf(stderr, "out of memory\n");
423 exit(1);
424 }
425 memset(d, 0, sizeof(struct footbridge_data));
426
427 /* DC21285 register access: */
428 memory_device_register(devinit->machine->memory, devinit->name,
429 devinit->addr, DEV_FOOTBRIDGE_LENGTH,
430 dev_footbridge_access, d, DM_DEFAULT, NULL);
431
432 /* ISA interrupt status/acknowledgement: */
433 memory_device_register(devinit->machine->memory, "footbridge_isa",
434 0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);
435
436 /* The "fcom" console: */
437 d->console_handle = console_start_slave(devinit->machine, "fcom");
438
439 /* A PCI bus: */
440 d->pcibus = bus_pci_init(
441 devinit->irq_nr, /* PCI controller irq */
442 0x7c000000, /* PCI device io offset */
443 0x80000000, /* PCI device mem offset */
444 0x00000000, /* PCI port base */
445 0x00000000, /* PCI mem base */
446 0, /* PCI irq base: TODO */
447 0x7c000000, /* ISA port base */
448 0x80000000, /* ISA mem base */
449 32); /* ISA port base */
450
451 /* ... with some default devices for known machine types: */
452 switch (devinit->machine->machine_type) {
453 case MACHINE_CATS:
454 bus_pci_add(devinit->machine, d->pcibus,
455 devinit->machine->memory, 0xc0, 7, 0, "ali_m1543");
456 bus_pci_add(devinit->machine, d->pcibus,
457 devinit->machine->memory, 0xc0, 10, 0, "dec21143");
458 bus_pci_add(devinit->machine, d->pcibus,
459 devinit->machine->memory, 0xc0, 16, 0, "ali_m5229");
460 break;
461 case MACHINE_NETWINDER:
462 bus_pci_add(devinit->machine, d->pcibus,
463 devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");
464 bus_pci_add(devinit->machine, d->pcibus,
465 devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");
466 break;
467 default:fatal("footbridge: unimplemented machine type.\n");
468 exit(1);
469 }
470
471 /* PCI configuration space: */
472 memory_device_register(devinit->machine->memory,
473 "footbridge_pci", pci_addr, 0x1000000,
474 dev_footbridge_pci_access, d, DM_DEFAULT, NULL);
475
476 /* Timer ticks: */
477 for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
478 d->timer_control[i] = TIMER_MODE_PERIODIC;
479 d->timer_load[i] = TIMER_MAX_VAL;
480 }
481 machine_add_tickfunction(devinit->machine,
482 dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT);
483
484 devinit->return_ptr = d;
485 return 1;
486 }
487

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