/[gxemul]/trunk/src/devices/dev_footbridge.c
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Contents of /trunk/src/devices/dev_footbridge.c

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 12491 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============
1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_footbridge.c,v 1.43 2006/03/04 12:38:47 debug Exp $
29 *
30 * Footbridge. Used in Netwinder and Cats.
31 *
32 * TODO:
33 * o) Add actual support for the fcom serial port.
34 * o) FIQs.
35 * o) Pretty much everything else as well :) (This entire thing
36 * is a quick hack to work primarily with NetBSD and OpenBSD
37 * as a guest OS.)
38 */
39
40 #include <stdio.h>
41 #include <stdlib.h>
42 #include <string.h>
43
44 #include "bus_pci.h"
45 #include "console.h"
46 #include "cpu.h"
47 #include "device.h"
48 #include "devices.h"
49 #include "machine.h"
50 #include "memory.h"
51 #include "misc.h"
52
53
54 #include "dc21285reg.h"
55
56 #define DEV_FOOTBRIDGE_TICK_SHIFT 14
57 #define DEV_FOOTBRIDGE_LENGTH 0x400
58 #define TIMER_POLL_THRESHOLD 15
59
60
61 /*
62 * dev_footbridge_tick():
63 *
64 * The 4 footbridge timers should decrease every now and then, and cause
65 * interrupts. Periodic interrupts restart as soon as they are acknowledged,
66 * non-periodic interrupts need to be "reloaded" to restart.
67 */
68 void dev_footbridge_tick(struct cpu *cpu, void *extra)
69 {
70 int i;
71 struct footbridge_data *d = (struct footbridge_data *) extra;
72
73 if (!d->timer_being_read)
74 d->timer_poll_mode = 0;
75
76 for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
77 unsigned int amount = 1 << DEV_FOOTBRIDGE_TICK_SHIFT;
78 if (d->timer_control[i] & TIMER_FCLK_16)
79 amount >>= 4;
80 else if (d->timer_control[i] & TIMER_FCLK_256)
81 amount >>= 8;
82
83 if (d->timer_tick_countdown[i] == 0)
84 continue;
85
86 if (d->timer_value[i] > amount)
87 d->timer_value[i] -= amount;
88 else
89 d->timer_value[i] = 0;
90
91 if (d->timer_value[i] == 0) {
92 d->timer_tick_countdown[i] --;
93 if (d->timer_tick_countdown[i] > 0)
94 continue;
95
96 if (d->timer_control[i] & TIMER_ENABLE)
97 cpu_interrupt(cpu, IRQ_TIMER_1 + i);
98 d->timer_tick_countdown[i] = 0;
99 }
100 }
101 }
102
103
104 /*
105 * dev_footbridge_isa_access():
106 *
107 * Reading the byte at 0x79000000 is a quicker way to figure out which ISA
108 * interrupt has occurred (and acknowledging it at the same time), than
109 * dealing with the legacy 0x20/0xa0 ISA ports.
110 */
111 DEVICE_ACCESS(footbridge_isa)
112 {
113 /* struct footbridge_data *d = extra; */
114 uint64_t idata = 0, odata = 0;
115 int x;
116
117 if (writeflag == MEM_WRITE) {
118 idata = memory_readmax64(cpu, data, len);
119 fatal("[ footbridge_isa: WARNING/TODO: write! ]\n");
120 }
121
122 x = cpu->machine->isa_pic_data.last_int;
123 if (x == 0)
124 cpu_interrupt_ack(cpu, 32 + x);
125
126 if (x < 8)
127 odata = cpu->machine->isa_pic_data.pic1->irq_base + x;
128 else
129 odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8;
130
131 if (writeflag == MEM_READ)
132 memory_writemax64(cpu, data, len, odata);
133
134 return 1;
135 }
136
137
138 /*
139 * dev_footbridge_pci_access():
140 *
141 * The Footbridge PCI configuration space is implemented as a direct memory
142 * space (i.e. not one port for addr and one port for data). This function
143 * translates that into bus_pci calls.
144 */
145 DEVICE_ACCESS(footbridge_pci)
146 {
147 struct footbridge_data *d = extra;
148 uint64_t idata = 0, odata = 0;
149 int bus, dev, func, reg;
150
151 if (writeflag == MEM_WRITE)
152 idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
153
154 /* Decompose the (direct) address into its components: */
155 bus_pci_decompose_1(relative_addr, &bus, &dev, &func, &reg);
156 bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg);
157
158 if (bus == 255) {
159 fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"
160 " pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc);
161 exit(1);
162 }
163
164 debug("[ footbridge pci: %s bus %i, device %i, function %i, register "
165 "%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus,
166 dev, func, reg);
167
168 bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ?
169 &odata : &idata, len, writeflag);
170
171 if (writeflag == MEM_READ)
172 memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
173
174 return 1;
175 }
176
177
178 /*
179 * dev_footbridge_access():
180 *
181 * The DC21285 registers.
182 */
183 DEVICE_ACCESS(footbridge)
184 {
185 struct footbridge_data *d = extra;
186 uint64_t idata = 0, odata = 0;
187 int timer_nr = 0;
188
189 if (writeflag == MEM_WRITE)
190 idata = memory_readmax64(cpu, data, len);
191
192 if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) {
193 timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1);
194 relative_addr &= ~0x060;
195 }
196
197 switch (relative_addr) {
198
199 case VENDOR_ID:
200 odata = 0x1011; /* DC21285_VENDOR_ID */
201 break;
202
203 case DEVICE_ID:
204 odata = 0x1065; /* DC21285_DEVICE_ID */
205 break;
206
207 case 0x04:
208 case 0x0c:
209 case 0x10:
210 case 0x14:
211 case 0x18:
212 /* TODO. Written to by Linux. */
213 break;
214
215 case REVISION:
216 odata = 3; /* footbridge revision number */
217 break;
218
219 case PCI_ADDRESS_EXTENSION:
220 /* TODO: Written to by Linux. */
221 if (writeflag == MEM_WRITE && idata != 0)
222 fatal("[ footbridge: TODO: write to PCI_ADDRESS_"
223 "EXTENSION: 0x%llx ]\n", (long long)idata);
224 break;
225
226 case SA_CONTROL:
227 /* Read by Linux: */
228 odata = PCI_CENTRAL_FUNCTION;
229 break;
230
231 case UART_DATA:
232 if (writeflag == MEM_WRITE)
233 console_putchar(d->console_handle, idata);
234 break;
235
236 case UART_RX_STAT:
237 /* TODO */
238 odata = 0;
239 break;
240
241 case UART_FLAGS:
242 odata = UART_TX_EMPTY;
243 break;
244
245 case IRQ_STATUS:
246 if (writeflag == MEM_READ)
247 odata = d->irq_status & d->irq_enable;
248 else {
249 fatal("[ WARNING: footbridge write to irq status? ]\n");
250 exit(1);
251 }
252 break;
253
254 case IRQ_RAW_STATUS:
255 if (writeflag == MEM_READ)
256 odata = d->irq_status;
257 else {
258 fatal("[ footbridge write to irq_raw_status ]\n");
259 exit(1);
260 }
261 break;
262
263 case IRQ_ENABLE_SET:
264 if (writeflag == MEM_WRITE) {
265 d->irq_enable |= idata;
266 cpu_interrupt(cpu, 64);
267 } else {
268 odata = d->irq_enable;
269 fatal("[ WARNING: footbridge read from "
270 "ENABLE SET? ]\n");
271 exit(1);
272 }
273 break;
274
275 case IRQ_ENABLE_CLEAR:
276 if (writeflag == MEM_WRITE) {
277 d->irq_enable &= ~idata;
278 cpu_interrupt(cpu, 64);
279 } else {
280 odata = d->irq_enable;
281 fatal("[ WARNING: footbridge read from "
282 "ENABLE CLEAR? ]\n");
283 exit(1);
284 }
285 break;
286
287 case FIQ_STATUS:
288 if (writeflag == MEM_READ)
289 odata = d->fiq_status & d->fiq_enable;
290 else {
291 fatal("[ WARNING: footbridge write to fiq status? ]\n");
292 exit(1);
293 }
294 break;
295
296 case FIQ_RAW_STATUS:
297 if (writeflag == MEM_READ)
298 odata = d->fiq_status;
299 else {
300 fatal("[ footbridge write to fiq_raw_status ]\n");
301 exit(1);
302 }
303 break;
304
305 case FIQ_ENABLE_SET:
306 if (writeflag == MEM_WRITE)
307 d->fiq_enable |= idata;
308 break;
309
310 case FIQ_ENABLE_CLEAR:
311 if (writeflag == MEM_WRITE)
312 d->fiq_enable &= ~idata;
313 break;
314
315 case TIMER_1_LOAD:
316 if (writeflag == MEM_READ)
317 odata = d->timer_load[timer_nr];
318 else {
319 d->timer_value[timer_nr] =
320 d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;
321 debug("[ footbridge: timer %i (1-based), value %i ]\n",
322 timer_nr + 1, (int)d->timer_value[timer_nr]);
323 d->timer_tick_countdown[timer_nr] = 1;
324 cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);
325 }
326 break;
327
328 case TIMER_1_VALUE:
329 if (writeflag == MEM_READ) {
330 /*
331 * NOTE/TODO: This is INCORRECT but speeds up NetBSD
332 * and OpenBSD boot sequences: if the timer is polled
333 * "very often" (such as during bootup), then this
334 * causes the timers to expire quickly.
335 */
336 d->timer_being_read = 1;
337 d->timer_poll_mode ++;
338 if (d->timer_poll_mode >= TIMER_POLL_THRESHOLD) {
339 d->timer_poll_mode = TIMER_POLL_THRESHOLD;
340 dev_footbridge_tick(cpu, d);
341 dev_footbridge_tick(cpu, d);
342 dev_footbridge_tick(cpu, d);
343 }
344 odata = d->timer_value[timer_nr];
345 d->timer_being_read = 0;
346 } else
347 d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;
348 break;
349
350 case TIMER_1_CONTROL:
351 if (writeflag == MEM_READ)
352 odata = d->timer_control[timer_nr];
353 else {
354 d->timer_control[timer_nr] = idata;
355 if (idata & TIMER_FCLK_16 &&
356 idata & TIMER_FCLK_256) {
357 fatal("TODO: footbridge timer: "
358 "both 16 and 256?\n");
359 exit(1);
360 }
361 if (idata & TIMER_ENABLE) {
362 d->timer_value[timer_nr] =
363 d->timer_load[timer_nr];
364 d->timer_tick_countdown[timer_nr] = 1;
365 }
366 cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);
367 }
368 break;
369
370 case TIMER_1_CLEAR:
371 if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {
372 d->timer_value[timer_nr] = d->timer_load[timer_nr];
373 d->timer_tick_countdown[timer_nr] = 1;
374 }
375 cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);
376 break;
377
378 default:if (writeflag == MEM_READ) {
379 fatal("[ footbridge: read from 0x%x ]\n",
380 (int)relative_addr);
381 } else {
382 fatal("[ footbridge: write to 0x%x: 0x%llx ]\n",
383 (int)relative_addr, (long long)idata);
384 }
385 }
386
387 if (writeflag == MEM_READ)
388 memory_writemax64(cpu, data, len, odata);
389
390 return 1;
391 }
392
393
394 DEVINIT(footbridge)
395 {
396 struct footbridge_data *d;
397 uint64_t pci_addr = 0x7b000000;
398 int i;
399
400 d = malloc(sizeof(struct footbridge_data));
401 if (d == NULL) {
402 fprintf(stderr, "out of memory\n");
403 exit(1);
404 }
405 memset(d, 0, sizeof(struct footbridge_data));
406
407 /* DC21285 register access: */
408 memory_device_register(devinit->machine->memory, devinit->name,
409 devinit->addr, DEV_FOOTBRIDGE_LENGTH,
410 dev_footbridge_access, d, DM_DEFAULT, NULL);
411
412 /* ISA interrupt status/acknowledgement: */
413 memory_device_register(devinit->machine->memory, "footbridge_isa",
414 0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);
415
416 /* The "fcom" console: */
417 d->console_handle = console_start_slave(devinit->machine, "fcom", 0);
418
419 /* A PCI bus: */
420 d->pcibus = bus_pci_init(
421 devinit->machine,
422 devinit->irq_nr, /* PCI controller irq */
423 0x7c000000, /* PCI device io offset */
424 0x80000000, /* PCI device mem offset */
425 0x00000000, /* PCI port base */
426 0x00000000, /* PCI mem base */
427 0, /* PCI irq base: TODO */
428 0x7c000000, /* ISA port base */
429 0x80000000, /* ISA mem base */
430 32); /* ISA port base */
431
432 /* ... with some default devices for known machine types: */
433 switch (devinit->machine->machine_type) {
434 case MACHINE_CATS:
435 bus_pci_add(devinit->machine, d->pcibus,
436 devinit->machine->memory, 0xc0, 7, 0, "ali_m1543");
437 bus_pci_add(devinit->machine, d->pcibus,
438 devinit->machine->memory, 0xc0, 10, 0, "dec21143");
439 bus_pci_add(devinit->machine, d->pcibus,
440 devinit->machine->memory, 0xc0, 16, 0, "ali_m5229");
441 break;
442 case MACHINE_NETWINDER:
443 bus_pci_add(devinit->machine, d->pcibus,
444 devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");
445 bus_pci_add(devinit->machine, d->pcibus,
446 devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");
447 break;
448 default:fatal("footbridge: unimplemented machine type.\n");
449 exit(1);
450 }
451
452 /* PCI configuration space: */
453 memory_device_register(devinit->machine->memory,
454 "footbridge_pci", pci_addr, 0x1000000,
455 dev_footbridge_pci_access, d, DM_DEFAULT, NULL);
456
457 /* Timer ticks: */
458 for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
459 d->timer_control[i] = TIMER_MODE_PERIODIC;
460 d->timer_load[i] = TIMER_MAX_VAL;
461 }
462 machine_add_tickfunction(devinit->machine,
463 dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT, 0.0);
464
465 devinit->return_ptr = d;
466 return 1;
467 }
468
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