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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_footbridge.c,v 1.48 2006/09/30 10:09:19 debug Exp $ |
* $Id: dev_footbridge.c,v 1.55 2007/02/03 16:18:56 debug Exp $ |
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* |
* |
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* Footbridge. Used in Netwinder and Cats. |
* Footbridge. Used in Netwinder and Cats. |
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* |
* |
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* o) FIQs. |
* o) FIQs. |
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* o) Pretty much everything else as well :) (This entire thing |
* o) Pretty much everything else as well :) (This entire thing |
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* is a quick hack to work primarily with NetBSD and OpenBSD |
* is a quick hack to work primarily with NetBSD and OpenBSD |
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* as a guest OS.) |
* as guest OSes.) |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#define DEV_FOOTBRIDGE_TICK_SHIFT 14 |
#define DEV_FOOTBRIDGE_TICK_SHIFT 14 |
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#define DEV_FOOTBRIDGE_LENGTH 0x400 |
#define DEV_FOOTBRIDGE_LENGTH 0x400 |
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#define N_FOOTBRIDGE_TIMERS 4 |
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struct footbridge_data { |
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struct interrupt irq; |
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struct pci_data *pcibus; |
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int console_handle; |
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uint32_t timer_load[N_FOOTBRIDGE_TIMERS]; |
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uint32_t timer_value[N_FOOTBRIDGE_TIMERS]; |
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uint32_t timer_control[N_FOOTBRIDGE_TIMERS]; |
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struct interrupt timer_irq[N_FOOTBRIDGE_TIMERS]; |
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struct timer *timer[N_FOOTBRIDGE_TIMERS]; |
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int pending_timer_interrupts[N_FOOTBRIDGE_TIMERS]; |
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int irq_asserted; |
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uint32_t irq_status; |
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uint32_t irq_enable; |
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uint32_t fiq_status; |
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uint32_t fiq_enable; |
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}; |
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static void timer_tick0(struct timer *t, void *extra) |
static void timer_tick0(struct timer *t, void *extra) |
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{ ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; } |
{ ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; } |
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freq /= (double)cycles; |
freq /= (double)cycles; |
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d->timer_value[timer_nr] = d->timer_load[timer_nr]; |
d->timer_value[timer_nr] = d->timer_load[timer_nr]; |
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d->timer_tick_countdown[timer_nr] = 1; |
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/* printf("%i: %i -> %f Hz\n", timer_nr, |
/* printf("%i: %i -> %f Hz\n", timer_nr, |
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d->timer_load[timer_nr], freq); */ |
d->timer_load[timer_nr], freq); */ |
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if (d->timer_control[i] & TIMER_ENABLE) { |
if (d->timer_control[i] & TIMER_ENABLE) { |
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if (d->pending_timer_interrupts[i] > 0) { |
if (d->pending_timer_interrupts[i] > 0) { |
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d->timer_value[i] = random() % d->timer_load[i]; |
d->timer_value[i] = random() % d->timer_load[i]; |
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cpu_interrupt(cpu, IRQ_TIMER_1 + i); |
INTERRUPT_ASSERT(d->timer_irq[i]); |
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} |
} |
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} |
} |
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} |
} |
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/* |
/* |
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* footbridge_interrupt_assert(): |
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*/ |
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void footbridge_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct footbridge_data *d = (struct footbridge_data *) interrupt->extra; |
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d->irq_status |= interrupt->line; |
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if ((d->irq_status & d->irq_enable) && !d->irq_asserted) { |
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d->irq_asserted = 1; |
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INTERRUPT_ASSERT(d->irq); |
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} |
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} |
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/* |
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* footbridge_interrupt_deassert(): |
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*/ |
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void footbridge_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct footbridge_data *d = (struct footbridge_data *) interrupt->extra; |
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d->irq_status &= ~interrupt->line; |
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if (!(d->irq_status & d->irq_enable) && d->irq_asserted) { |
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d->irq_asserted = 0; |
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INTERRUPT_DEASSERT(d->irq); |
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} |
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} |
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/* |
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* dev_footbridge_isa_access(): |
* dev_footbridge_isa_access(): |
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* |
* |
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* Reading the byte at 0x79000000 is a quicker way to figure out which ISA |
* Reading the byte at 0x79000000 is a quicker way to figure out which ISA |
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} |
} |
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x = cpu->machine->isa_pic_data.last_int; |
x = cpu->machine->isa_pic_data.last_int; |
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if (x == 0) |
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cpu_interrupt_ack(cpu, 32 + x); |
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if (x < 8) |
if (x < 8) |
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odata = cpu->machine->isa_pic_data.pic1->irq_base + x; |
odata = cpu->machine->isa_pic_data.pic1->irq_base + x; |
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else |
else |
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case IRQ_ENABLE_SET: |
case IRQ_ENABLE_SET: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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d->irq_enable |= idata; |
d->irq_enable |= idata; |
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cpu_interrupt(cpu, 64); |
if (d->irq_status & d->irq_enable) |
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INTERRUPT_ASSERT(d->irq); |
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else |
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INTERRUPT_DEASSERT(d->irq); |
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} else { |
} else { |
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odata = d->irq_enable; |
odata = d->irq_enable; |
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fatal("[ WARNING: footbridge read from " |
fatal("[ WARNING: footbridge read from " |
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case IRQ_ENABLE_CLEAR: |
case IRQ_ENABLE_CLEAR: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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d->irq_enable &= ~idata; |
d->irq_enable &= ~idata; |
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cpu_interrupt(cpu, 64); |
if (d->irq_status & d->irq_enable) |
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INTERRUPT_ASSERT(d->irq); |
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else |
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INTERRUPT_DEASSERT(d->irq); |
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} else { |
} else { |
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odata = d->irq_enable; |
odata = d->irq_enable; |
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fatal("[ WARNING: footbridge read from " |
fatal("[ WARNING: footbridge read from " |
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/* debug("[ footbridge: timer %i (1-based), " |
/* debug("[ footbridge: timer %i (1-based), " |
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"value %i ]\n", timer_nr + 1, |
"value %i ]\n", timer_nr + 1, |
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(int)d->timer_value[timer_nr]); */ |
(int)d->timer_value[timer_nr]); */ |
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cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]); |
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} |
} |
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break; |
break; |
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} else { |
} else { |
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d->pending_timer_interrupts[timer_nr] = 0; |
d->pending_timer_interrupts[timer_nr] = 0; |
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} |
} |
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cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]); |
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} |
} |
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break; |
break; |
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d->pending_timer_interrupts[timer_nr] --; |
d->pending_timer_interrupts[timer_nr] --; |
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} |
} |
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cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]); |
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break; |
break; |
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default:if (writeflag == MEM_READ) { |
default:if (writeflag == MEM_READ) { |
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DEVINIT(footbridge) |
DEVINIT(footbridge) |
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{ |
{ |
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struct footbridge_data *d; |
struct footbridge_data *d; |
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char irq_path[300], irq_path_isa[300]; |
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uint64_t pci_addr = 0x7b000000; |
uint64_t pci_addr = 0x7b000000; |
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int i; |
int i; |
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} |
} |
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memset(d, 0, sizeof(struct footbridge_data)); |
memset(d, 0, sizeof(struct footbridge_data)); |
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/* Connect to the CPU which this footbridge will interrupt: */ |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
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/* DC21285 register access: */ |
/* DC21285 register access: */ |
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memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_FOOTBRIDGE_LENGTH, |
devinit->addr, DEV_FOOTBRIDGE_LENGTH, |
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/* The "fcom" console: */ |
/* The "fcom" console: */ |
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d->console_handle = console_start_slave(devinit->machine, "fcom", 0); |
d->console_handle = console_start_slave(devinit->machine, "fcom", 0); |
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/* Register 32 footbridge interrupts: */ |
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snprintf(irq_path, sizeof(irq_path), "%s.footbridge", |
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devinit->interrupt_path); |
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for (i=0; i<32; i++) { |
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struct interrupt interrupt_template; |
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char tmpstr[200]; |
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memset(&interrupt_template, 0, sizeof(interrupt_template)); |
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interrupt_template.line = 1 << i; |
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snprintf(tmpstr, sizeof(tmpstr), "%s.%i", irq_path, i); |
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interrupt_template.name = tmpstr; |
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interrupt_template.extra = d; |
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interrupt_template.interrupt_assert = |
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footbridge_interrupt_assert; |
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interrupt_template.interrupt_deassert = |
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footbridge_interrupt_deassert; |
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interrupt_handler_register(&interrupt_template); |
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/* Connect locally to some interrupts: */ |
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if (i>=IRQ_TIMER_1 && i<=IRQ_TIMER_4) |
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INTERRUPT_CONNECT(tmpstr, d->timer_irq[i-IRQ_TIMER_1]); |
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} |
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switch (devinit->machine->machine_type) { |
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case MACHINE_CATS: |
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snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.10", irq_path); |
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break; |
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case MACHINE_NETWINDER: |
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snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.11", irq_path); |
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break; |
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default:fatal("footbridge unimpl machine type\n"); |
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exit(1); |
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} |
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/* A PCI bus: */ |
/* A PCI bus: */ |
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d->pcibus = bus_pci_init( |
d->pcibus = bus_pci_init( |
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devinit->machine, |
devinit->machine, |
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devinit->irq_nr, /* PCI controller irq */ |
irq_path, |
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0x7c000000, /* PCI device io offset */ |
0x7c000000, /* PCI device io offset */ |
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0x80000000, /* PCI device mem offset */ |
0x80000000, /* PCI device mem offset */ |
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0x00000000, /* PCI port base */ |
0x00000000, /* PCI port base */ |
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0x00000000, /* PCI mem base */ |
0x00000000, /* PCI mem base */ |
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0, /* PCI irq base: TODO */ |
irq_path, /* PCI irq base */ |
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0x7c000000, /* ISA port base */ |
0x7c000000, /* ISA port base */ |
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0x80000000, /* ISA mem base */ |
0x80000000, /* ISA mem base */ |
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32); /* ISA port base */ |
irq_path_isa); /* ISA port base */ |
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/* ... with some default devices for known machine types: */ |
/* ... with some default devices for known machine types: */ |
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switch (devinit->machine->machine_type) { |
switch (devinit->machine->machine_type) { |
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machine_add_tickfunction(devinit->machine, |
machine_add_tickfunction(devinit->machine, |
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dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT, 0.0); |
dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT, 0.0); |
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devinit->return_ptr = d; |
devinit->return_ptr = d->pcibus; |
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return 1; |
return 1; |
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} |
} |
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