/[gxemul]/trunk/src/devices/dev_footbridge.c
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Annotation of /trunk/src/devices/dev_footbridge.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 15832 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 dpavlin 14 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: dev_footbridge.c,v 1.57 2007/06/15 19:11:15 debug Exp $
29 dpavlin 14 *
30 dpavlin 42 * COMMENT: DC21285 "Footbridge" controller; used in Netwinder and Cats
31 dpavlin 14 *
32 dpavlin 20 * TODO:
33 dpavlin 14 * o) Add actual support for the fcom serial port.
34     * o) FIQs.
35 dpavlin 22 * o) Pretty much everything else as well :) (This entire thing
36     * is a quick hack to work primarily with NetBSD and OpenBSD
37 dpavlin 34 * as guest OSes.)
38 dpavlin 14 */
39    
40     #include <stdio.h>
41     #include <stdlib.h>
42     #include <string.h>
43    
44     #include "bus_pci.h"
45     #include "console.h"
46     #include "cpu.h"
47     #include "device.h"
48 dpavlin 22 #include "devices.h"
49 dpavlin 14 #include "machine.h"
50     #include "memory.h"
51     #include "misc.h"
52 dpavlin 32 #include "timer.h"
53 dpavlin 14
54    
55     #include "dc21285reg.h"
56    
57     #define DEV_FOOTBRIDGE_TICK_SHIFT 14
58     #define DEV_FOOTBRIDGE_LENGTH 0x400
59    
60 dpavlin 34 #define N_FOOTBRIDGE_TIMERS 4
61 dpavlin 14
62 dpavlin 34 struct footbridge_data {
63     struct interrupt irq;
64    
65     struct pci_data *pcibus;
66    
67     int console_handle;
68    
69     uint32_t timer_load[N_FOOTBRIDGE_TIMERS];
70     uint32_t timer_value[N_FOOTBRIDGE_TIMERS];
71     uint32_t timer_control[N_FOOTBRIDGE_TIMERS];
72    
73     struct interrupt timer_irq[N_FOOTBRIDGE_TIMERS];
74     struct timer *timer[N_FOOTBRIDGE_TIMERS];
75     int pending_timer_interrupts[N_FOOTBRIDGE_TIMERS];
76    
77     int irq_asserted;
78    
79     uint32_t irq_status;
80     uint32_t irq_enable;
81    
82     uint32_t fiq_status;
83     uint32_t fiq_enable;
84     };
85    
86    
87 dpavlin 32 static void timer_tick0(struct timer *t, void *extra)
88     { ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; }
89     static void timer_tick1(struct timer *t, void *extra)
90     { ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; }
91     static void timer_tick2(struct timer *t, void *extra)
92     { ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; }
93     static void timer_tick3(struct timer *t, void *extra)
94     { ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; }
95    
96    
97     static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d,
98     int timer_nr)
99     {
100     double freq = (double)cpu->machine->emulated_hz;
101     int cycles = d->timer_load[timer_nr];
102    
103     if (d->timer_control[timer_nr] & TIMER_FCLK_16)
104     cycles <<= 4;
105     else if (d->timer_control[timer_nr] & TIMER_FCLK_256)
106     cycles <<= 8;
107     freq /= (double)cycles;
108    
109     d->timer_value[timer_nr] = d->timer_load[timer_nr];
110    
111     /* printf("%i: %i -> %f Hz\n", timer_nr,
112     d->timer_load[timer_nr], freq); */
113    
114     if (d->timer[timer_nr] == NULL) {
115     switch (timer_nr) {
116     case 0: d->timer[0] = timer_add(freq, timer_tick0, d); break;
117     case 1: d->timer[1] = timer_add(freq, timer_tick1, d); break;
118     case 2: d->timer[2] = timer_add(freq, timer_tick2, d); break;
119     case 3: d->timer[3] = timer_add(freq, timer_tick3, d); break;
120     }
121     } else {
122     timer_update_frequency(d->timer[timer_nr], freq);
123     }
124     }
125    
126    
127 dpavlin 14 /*
128 dpavlin 32 * The 4 footbridge timers should decrease and cause interrupts. Periodic
129     * interrupts restart as soon as they are acknowledged, non-periodic
130     * interrupts need to be "reloaded" to restart.
131     *
132     * TODO: Hm. I thought I had solved this, but it didn't quite work.
133     * This needs to be re-checked against documentation, sometime.
134 dpavlin 14 */
135 dpavlin 42 DEVICE_TICK(footbridge)
136 dpavlin 14 {
137 dpavlin 42 struct footbridge_data *d = extra;
138 dpavlin 14 int i;
139    
140     for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
141 dpavlin 32 if (d->timer_control[i] & TIMER_ENABLE) {
142     if (d->pending_timer_interrupts[i] > 0) {
143     d->timer_value[i] = random() % d->timer_load[i];
144 dpavlin 34 INTERRUPT_ASSERT(d->timer_irq[i]);
145 dpavlin 32 }
146 dpavlin 14 }
147     }
148     }
149    
150    
151     /*
152 dpavlin 34 * footbridge_interrupt_assert():
153     */
154     void footbridge_interrupt_assert(struct interrupt *interrupt)
155     {
156     struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
157     d->irq_status |= interrupt->line;
158    
159     if ((d->irq_status & d->irq_enable) && !d->irq_asserted) {
160     d->irq_asserted = 1;
161     INTERRUPT_ASSERT(d->irq);
162     }
163     }
164    
165    
166     /*
167     * footbridge_interrupt_deassert():
168     */
169     void footbridge_interrupt_deassert(struct interrupt *interrupt)
170     {
171     struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
172     d->irq_status &= ~interrupt->line;
173    
174     if (!(d->irq_status & d->irq_enable) && d->irq_asserted) {
175     d->irq_asserted = 0;
176     INTERRUPT_DEASSERT(d->irq);
177     }
178     }
179    
180    
181     /*
182 dpavlin 20 * Reading the byte at 0x79000000 is a quicker way to figure out which ISA
183     * interrupt has occurred (and acknowledging it at the same time), than
184     * dealing with the legacy 0x20/0xa0 ISA ports.
185 dpavlin 14 */
186 dpavlin 22 DEVICE_ACCESS(footbridge_isa)
187 dpavlin 14 {
188     /* struct footbridge_data *d = extra; */
189     uint64_t idata = 0, odata = 0;
190     int x;
191    
192 dpavlin 18 if (writeflag == MEM_WRITE) {
193     idata = memory_readmax64(cpu, data, len);
194 dpavlin 14 fatal("[ footbridge_isa: WARNING/TODO: write! ]\n");
195 dpavlin 18 }
196 dpavlin 14
197 dpavlin 20 x = cpu->machine->isa_pic_data.last_int;
198     if (x < 8)
199     odata = cpu->machine->isa_pic_data.pic1->irq_base + x;
200     else
201     odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8;
202 dpavlin 14
203     if (writeflag == MEM_READ)
204     memory_writemax64(cpu, data, len, odata);
205    
206     return 1;
207     }
208    
209    
210     /*
211 dpavlin 30 * Reset pin at ISA port 0x338, at least in the NetWinder:
212     *
213     * TODO: NOT WORKING YET!
214     */
215     DEVICE_ACCESS(footbridge_reset)
216     {
217     uint64_t idata = 0;
218    
219     if (writeflag == MEM_WRITE) {
220     idata = memory_readmax64(cpu, data, len);
221     if (idata & 0x40) {
222     debug("[ footbridge_reset: GP16: Halting. ]\n");
223     cpu->running = 0;
224     exit(1);
225     }
226     }
227    
228     return 1;
229     }
230    
231    
232     /*
233 dpavlin 22 * The Footbridge PCI configuration space is implemented as a direct memory
234     * space (i.e. not one port for addr and one port for data). This function
235     * translates that into bus_pci calls.
236 dpavlin 14 */
237 dpavlin 22 DEVICE_ACCESS(footbridge_pci)
238 dpavlin 14 {
239     struct footbridge_data *d = extra;
240     uint64_t idata = 0, odata = 0;
241 dpavlin 22 int bus, dev, func, reg;
242 dpavlin 14
243 dpavlin 18 if (writeflag == MEM_WRITE)
244 dpavlin 22 idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
245 dpavlin 14
246 dpavlin 22 /* Decompose the (direct) address into its components: */
247     bus_pci_decompose_1(relative_addr, &bus, &dev, &func, &reg);
248     bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg);
249 dpavlin 14
250     if (bus == 255) {
251     fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"
252     " pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc);
253     exit(1);
254     }
255    
256 dpavlin 22 debug("[ footbridge pci: %s bus %i, device %i, function %i, register "
257     "%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus,
258     dev, func, reg);
259 dpavlin 14
260 dpavlin 22 bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ?
261     &odata : &idata, len, writeflag);
262 dpavlin 14
263     if (writeflag == MEM_READ)
264 dpavlin 22 memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
265 dpavlin 14
266     return 1;
267     }
268    
269    
270 dpavlin 22 DEVICE_ACCESS(footbridge)
271 dpavlin 14 {
272     struct footbridge_data *d = extra;
273     uint64_t idata = 0, odata = 0;
274     int timer_nr = 0;
275    
276 dpavlin 18 if (writeflag == MEM_WRITE)
277     idata = memory_readmax64(cpu, data, len);
278 dpavlin 14
279     if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) {
280     timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1);
281     relative_addr &= ~0x060;
282     }
283    
284     switch (relative_addr) {
285    
286     case VENDOR_ID:
287     odata = 0x1011; /* DC21285_VENDOR_ID */
288     break;
289    
290     case DEVICE_ID:
291     odata = 0x1065; /* DC21285_DEVICE_ID */
292     break;
293    
294 dpavlin 20 case 0x04:
295     case 0x0c:
296     case 0x10:
297     case 0x14:
298     case 0x18:
299     /* TODO. Written to by Linux. */
300     break;
301    
302 dpavlin 14 case REVISION:
303     odata = 3; /* footbridge revision number */
304     break;
305    
306 dpavlin 20 case PCI_ADDRESS_EXTENSION:
307     /* TODO: Written to by Linux. */
308     if (writeflag == MEM_WRITE && idata != 0)
309     fatal("[ footbridge: TODO: write to PCI_ADDRESS_"
310     "EXTENSION: 0x%llx ]\n", (long long)idata);
311     break;
312    
313 dpavlin 22 case SA_CONTROL:
314     /* Read by Linux: */
315     odata = PCI_CENTRAL_FUNCTION;
316     break;
317    
318 dpavlin 14 case UART_DATA:
319     if (writeflag == MEM_WRITE)
320     console_putchar(d->console_handle, idata);
321     break;
322    
323     case UART_RX_STAT:
324     /* TODO */
325     odata = 0;
326     break;
327    
328     case UART_FLAGS:
329     odata = UART_TX_EMPTY;
330     break;
331    
332     case IRQ_STATUS:
333     if (writeflag == MEM_READ)
334     odata = d->irq_status & d->irq_enable;
335     else {
336     fatal("[ WARNING: footbridge write to irq status? ]\n");
337     exit(1);
338     }
339     break;
340    
341     case IRQ_RAW_STATUS:
342     if (writeflag == MEM_READ)
343     odata = d->irq_status;
344     else {
345     fatal("[ footbridge write to irq_raw_status ]\n");
346     exit(1);
347     }
348     break;
349    
350     case IRQ_ENABLE_SET:
351     if (writeflag == MEM_WRITE) {
352     d->irq_enable |= idata;
353 dpavlin 34 if (d->irq_status & d->irq_enable)
354     INTERRUPT_ASSERT(d->irq);
355     else
356     INTERRUPT_DEASSERT(d->irq);
357 dpavlin 14 } else {
358 dpavlin 18 odata = d->irq_enable;
359 dpavlin 14 fatal("[ WARNING: footbridge read from "
360     "ENABLE SET? ]\n");
361     exit(1);
362     }
363     break;
364    
365     case IRQ_ENABLE_CLEAR:
366     if (writeflag == MEM_WRITE) {
367     d->irq_enable &= ~idata;
368 dpavlin 34 if (d->irq_status & d->irq_enable)
369     INTERRUPT_ASSERT(d->irq);
370     else
371     INTERRUPT_DEASSERT(d->irq);
372 dpavlin 14 } else {
373 dpavlin 18 odata = d->irq_enable;
374 dpavlin 14 fatal("[ WARNING: footbridge read from "
375     "ENABLE CLEAR? ]\n");
376     exit(1);
377     }
378     break;
379    
380     case FIQ_STATUS:
381     if (writeflag == MEM_READ)
382     odata = d->fiq_status & d->fiq_enable;
383     else {
384     fatal("[ WARNING: footbridge write to fiq status? ]\n");
385     exit(1);
386     }
387     break;
388    
389     case FIQ_RAW_STATUS:
390     if (writeflag == MEM_READ)
391     odata = d->fiq_status;
392     else {
393     fatal("[ footbridge write to fiq_raw_status ]\n");
394     exit(1);
395     }
396     break;
397    
398     case FIQ_ENABLE_SET:
399     if (writeflag == MEM_WRITE)
400     d->fiq_enable |= idata;
401     break;
402    
403     case FIQ_ENABLE_CLEAR:
404     if (writeflag == MEM_WRITE)
405     d->fiq_enable &= ~idata;
406     break;
407    
408     case TIMER_1_LOAD:
409     if (writeflag == MEM_READ)
410     odata = d->timer_load[timer_nr];
411     else {
412 dpavlin 32 d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;
413     reload_timer_value(cpu, d, timer_nr);
414     /* debug("[ footbridge: timer %i (1-based), "
415     "value %i ]\n", timer_nr + 1,
416     (int)d->timer_value[timer_nr]); */
417 dpavlin 34 INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
418 dpavlin 14 }
419     break;
420    
421     case TIMER_1_VALUE:
422 dpavlin 32 if (writeflag == MEM_READ)
423 dpavlin 14 odata = d->timer_value[timer_nr];
424 dpavlin 32 else
425 dpavlin 14 d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;
426     break;
427    
428     case TIMER_1_CONTROL:
429     if (writeflag == MEM_READ)
430     odata = d->timer_control[timer_nr];
431     else {
432     d->timer_control[timer_nr] = idata;
433     if (idata & TIMER_FCLK_16 &&
434     idata & TIMER_FCLK_256) {
435     fatal("TODO: footbridge timer: "
436     "both 16 and 256?\n");
437     exit(1);
438     }
439     if (idata & TIMER_ENABLE) {
440 dpavlin 32 reload_timer_value(cpu, d, timer_nr);
441     } else {
442     d->pending_timer_interrupts[timer_nr] = 0;
443 dpavlin 14 }
444 dpavlin 34 INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
445 dpavlin 14 }
446     break;
447    
448     case TIMER_1_CLEAR:
449     if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {
450 dpavlin 32 reload_timer_value(cpu, d, timer_nr);
451 dpavlin 14 }
452 dpavlin 32
453     if (d->pending_timer_interrupts[timer_nr] > 0) {
454     d->pending_timer_interrupts[timer_nr] --;
455     }
456    
457 dpavlin 34 INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
458 dpavlin 14 break;
459    
460     default:if (writeflag == MEM_READ) {
461     fatal("[ footbridge: read from 0x%x ]\n",
462     (int)relative_addr);
463     } else {
464     fatal("[ footbridge: write to 0x%x: 0x%llx ]\n",
465     (int)relative_addr, (long long)idata);
466     }
467     }
468    
469     if (writeflag == MEM_READ)
470     memory_writemax64(cpu, data, len, odata);
471    
472     return 1;
473     }
474    
475    
476 dpavlin 22 DEVINIT(footbridge)
477 dpavlin 14 {
478     struct footbridge_data *d;
479 dpavlin 34 char irq_path[300], irq_path_isa[300];
480 dpavlin 14 uint64_t pci_addr = 0x7b000000;
481     int i;
482    
483 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct footbridge_data)));
484 dpavlin 14 memset(d, 0, sizeof(struct footbridge_data));
485    
486 dpavlin 34 /* Connect to the CPU which this footbridge will interrupt: */
487     INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
488    
489 dpavlin 14 /* DC21285 register access: */
490     memory_device_register(devinit->machine->memory, devinit->name,
491     devinit->addr, DEV_FOOTBRIDGE_LENGTH,
492 dpavlin 20 dev_footbridge_access, d, DM_DEFAULT, NULL);
493 dpavlin 14
494 dpavlin 20 /* ISA interrupt status/acknowledgement: */
495 dpavlin 14 memory_device_register(devinit->machine->memory, "footbridge_isa",
496 dpavlin 20 0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);
497 dpavlin 14
498     /* The "fcom" console: */
499 dpavlin 22 d->console_handle = console_start_slave(devinit->machine, "fcom", 0);
500 dpavlin 14
501 dpavlin 34 /* Register 32 footbridge interrupts: */
502     snprintf(irq_path, sizeof(irq_path), "%s.footbridge",
503     devinit->interrupt_path);
504     for (i=0; i<32; i++) {
505     struct interrupt interrupt_template;
506     char tmpstr[200];
507    
508     memset(&interrupt_template, 0, sizeof(interrupt_template));
509     interrupt_template.line = 1 << i;
510     snprintf(tmpstr, sizeof(tmpstr), "%s.%i", irq_path, i);
511     interrupt_template.name = tmpstr;
512    
513     interrupt_template.extra = d;
514     interrupt_template.interrupt_assert =
515     footbridge_interrupt_assert;
516     interrupt_template.interrupt_deassert =
517     footbridge_interrupt_deassert;
518     interrupt_handler_register(&interrupt_template);
519    
520     /* Connect locally to some interrupts: */
521     if (i>=IRQ_TIMER_1 && i<=IRQ_TIMER_4)
522     INTERRUPT_CONNECT(tmpstr, d->timer_irq[i-IRQ_TIMER_1]);
523     }
524    
525     switch (devinit->machine->machine_type) {
526     case MACHINE_CATS:
527     snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.10", irq_path);
528     break;
529     case MACHINE_NETWINDER:
530     snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.11", irq_path);
531     break;
532     default:fatal("footbridge unimpl machine type\n");
533     exit(1);
534     }
535    
536 dpavlin 14 /* A PCI bus: */
537 dpavlin 20 d->pcibus = bus_pci_init(
538 dpavlin 22 devinit->machine,
539 dpavlin 34 irq_path,
540 dpavlin 20 0x7c000000, /* PCI device io offset */
541     0x80000000, /* PCI device mem offset */
542     0x00000000, /* PCI port base */
543     0x00000000, /* PCI mem base */
544 dpavlin 34 irq_path, /* PCI irq base */
545 dpavlin 20 0x7c000000, /* ISA port base */
546     0x80000000, /* ISA mem base */
547 dpavlin 34 irq_path_isa); /* ISA port base */
548 dpavlin 14
549     /* ... with some default devices for known machine types: */
550     switch (devinit->machine->machine_type) {
551     case MACHINE_CATS:
552     bus_pci_add(devinit->machine, d->pcibus,
553 dpavlin 20 devinit->machine->memory, 0xc0, 7, 0, "ali_m1543");
554 dpavlin 14 bus_pci_add(devinit->machine, d->pcibus,
555 dpavlin 20 devinit->machine->memory, 0xc0, 10, 0, "dec21143");
556     bus_pci_add(devinit->machine, d->pcibus,
557     devinit->machine->memory, 0xc0, 16, 0, "ali_m5229");
558 dpavlin 14 break;
559     case MACHINE_NETWINDER:
560     bus_pci_add(devinit->machine, d->pcibus,
561 dpavlin 20 devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");
562 dpavlin 14 bus_pci_add(devinit->machine, d->pcibus,
563 dpavlin 20 devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");
564 dpavlin 30 memory_device_register(devinit->machine->memory,
565     "footbridge_reset", 0x7c000338, 1,
566     dev_footbridge_reset_access, d, DM_DEFAULT, NULL);
567 dpavlin 14 break;
568     default:fatal("footbridge: unimplemented machine type.\n");
569     exit(1);
570     }
571    
572     /* PCI configuration space: */
573     memory_device_register(devinit->machine->memory,
574     "footbridge_pci", pci_addr, 0x1000000,
575 dpavlin 20 dev_footbridge_pci_access, d, DM_DEFAULT, NULL);
576 dpavlin 14
577     /* Timer ticks: */
578     for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
579     d->timer_control[i] = TIMER_MODE_PERIODIC;
580     d->timer_load[i] = TIMER_MAX_VAL;
581     }
582 dpavlin 42
583 dpavlin 14 machine_add_tickfunction(devinit->machine,
584 dpavlin 42 dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT);
585 dpavlin 14
586 dpavlin 34 devinit->return_ptr = d->pcibus;
587 dpavlin 14 return 1;
588     }
589    

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