/[gxemul]/trunk/src/devices/dev_footbridge.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 21 by dpavlin, Mon Oct 8 16:19:23 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: dev_footbridge.c,v 1.36 2005/11/21 09:17:26 debug Exp $   *  $Id: dev_footbridge.c,v 1.42 2006/02/09 20:02:59 debug Exp $
29   *   *
30   *  Footbridge. Used in Netwinder and Cats.   *  Footbridge. Used in Netwinder and Cats.
31   *   *
32   *  TODO:   *  TODO:
33   *      o)  Add actual support for the fcom serial port.   *      o)  Add actual support for the fcom serial port.
34   *      o)  FIQs.   *      o)  FIQs.
35     *      o)  Pretty much everything else as well :)  (This entire thing
36     *          is a quick hack to work primarily with NetBSD and OpenBSD
37     *          as a guest OS.)
38   */   */
39    
40  #include <stdio.h>  #include <stdio.h>
# Line 42  Line 45 
45  #include "console.h"  #include "console.h"
46  #include "cpu.h"  #include "cpu.h"
47  #include "device.h"  #include "device.h"
48  #include "devices.h"    /*  for struct footbridge_data  */  #include "devices.h"
49  #include "machine.h"  #include "machine.h"
50  #include "memory.h"  #include "memory.h"
51  #include "misc.h"  #include "misc.h"
# Line 71  void dev_footbridge_tick(struct cpu *cpu Line 74  void dev_footbridge_tick(struct cpu *cpu
74                  d->timer_poll_mode = 0;                  d->timer_poll_mode = 0;
75    
76          for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {          for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
77                  int amount = 1 << DEV_FOOTBRIDGE_TICK_SHIFT;                  unsigned int amount = 1 << DEV_FOOTBRIDGE_TICK_SHIFT;
78                  if (d->timer_control[i] & TIMER_FCLK_16)                  if (d->timer_control[i] & TIMER_FCLK_16)
79                          amount >>= 4;                          amount >>= 4;
80                  else if (d->timer_control[i] & TIMER_FCLK_256)                  else if (d->timer_control[i] & TIMER_FCLK_256)
# Line 105  void dev_footbridge_tick(struct cpu *cpu Line 108  void dev_footbridge_tick(struct cpu *cpu
108   *  interrupt has occurred (and acknowledging it at the same time), than   *  interrupt has occurred (and acknowledging it at the same time), than
109   *  dealing with the legacy 0x20/0xa0 ISA ports.   *  dealing with the legacy 0x20/0xa0 ISA ports.
110   */   */
111  int dev_footbridge_isa_access(struct cpu *cpu, struct memory *mem,  DEVICE_ACCESS(footbridge_isa)
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
112  {  {
113          /*  struct footbridge_data *d = extra;  */          /*  struct footbridge_data *d = extra;  */
114          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
# Line 137  int dev_footbridge_isa_access(struct cpu Line 138  int dev_footbridge_isa_access(struct cpu
138  /*  /*
139   *  dev_footbridge_pci_access():   *  dev_footbridge_pci_access():
140   *   *
141   *  The Footbridge PCI configuration space is not implemented as "address +   *  The Footbridge PCI configuration space is implemented as a direct memory
142   *  data port" pair, but instead a 24-bit (16 MB) chunk of physical memory   *  space (i.e. not one port for addr and one port for data). This function
143   *  decodes as the address. This function translates that into bus_pci_access   *  translates that into bus_pci calls.
  *  calls.  
144   */   */
145  int dev_footbridge_pci_access(struct cpu *cpu, struct memory *mem,  DEVICE_ACCESS(footbridge_pci)
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
146  {  {
147          struct footbridge_data *d = extra;          struct footbridge_data *d = extra;
148          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
149          int bus, device, function, regnr, res;          int bus, dev, func, reg;
         uint64_t pci_word;  
150    
151          if (writeflag == MEM_WRITE)          if (writeflag == MEM_WRITE)
152                  idata = memory_readmax64(cpu, data, len);                  idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
153    
154          bus      = (relative_addr >> 16) & 0xff;          /*  Decompose the (direct) address into its components:  */
155          device   = (relative_addr >> 11) & 0x1f;          bus_pci_decompose_1(relative_addr, &bus, &dev, &func, &reg);
156          function = (relative_addr >> 8) & 0x7;          bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg);
         regnr    = relative_addr & 0xff;  
157    
158          if (bus == 255) {          if (bus == 255) {
159                  fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"                  fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"
# Line 165  int dev_footbridge_pci_access(struct cpu Line 161  int dev_footbridge_pci_access(struct cpu
161                  exit(1);                  exit(1);
162          }          }
163    
164          debug("[ footbridge_pci: %s bus %i, device %i, function "          debug("[ footbridge pci: %s bus %i, device %i, function %i, register "
165              "%i, register %i ]\n", writeflag == MEM_READ? "read from"              "%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus,
166              : "write to", bus, device, function, regnr);              dev, func, reg);
   
         if (d->pcibus == NULL) {  
                 fatal("dev_footbridge_pci_access(): no PCI bus?\n");  
                 return 0;  
         }  
167    
168          pci_word = relative_addr & 0x00ffffff;          bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ?
169                &odata : &idata, len, writeflag);
         res = bus_pci_access(cpu, mem, BUS_PCI_ADDR,  
             &pci_word, sizeof(uint32_t), MEM_WRITE, d->pcibus);  
         if (writeflag == MEM_READ) {  
                 res = bus_pci_access(cpu, mem, BUS_PCI_DATA,  
                     &pci_word, len, MEM_READ, d->pcibus);  
                 odata = pci_word;  
         } else {  
                 pci_word = idata;  
                 res = bus_pci_access(cpu, mem, BUS_PCI_DATA,  
                     &pci_word, len, MEM_WRITE, d->pcibus);  
         }  
170    
171          if (writeflag == MEM_READ)          if (writeflag == MEM_READ)
172                  memory_writemax64(cpu, data, len, odata);                  memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
173    
174          return 1;          return 1;
175  }  }
# Line 200  int dev_footbridge_pci_access(struct cpu Line 180  int dev_footbridge_pci_access(struct cpu
180   *   *
181   *  The DC21285 registers.   *  The DC21285 registers.
182   */   */
183  int dev_footbridge_access(struct cpu *cpu, struct memory *mem,  DEVICE_ACCESS(footbridge)
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
184  {  {
185          struct footbridge_data *d = extra;          struct footbridge_data *d = extra;
186          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
# Line 245  int dev_footbridge_access(struct cpu *cp Line 223  int dev_footbridge_access(struct cpu *cp
223                              "EXTENSION: 0x%llx ]\n", (long long)idata);                              "EXTENSION: 0x%llx ]\n", (long long)idata);
224                  break;                  break;
225    
226            case SA_CONTROL:
227                    /*  Read by Linux:  */
228                    odata = PCI_CENTRAL_FUNCTION;
229                    break;
230    
231          case UART_DATA:          case UART_DATA:
232                  if (writeflag == MEM_WRITE)                  if (writeflag == MEM_WRITE)
233                          console_putchar(d->console_handle, idata);                          console_putchar(d->console_handle, idata);
# Line 408  int dev_footbridge_access(struct cpu *cp Line 391  int dev_footbridge_access(struct cpu *cp
391  }  }
392    
393    
394  /*  DEVINIT(footbridge)
  *  devinit_footbridge():  
  */  
 int devinit_footbridge(struct devinit *devinit)  
395  {  {
396          struct footbridge_data *d;          struct footbridge_data *d;
397          uint64_t pci_addr = 0x7b000000;          uint64_t pci_addr = 0x7b000000;
# Line 434  int devinit_footbridge(struct devinit *d Line 414  int devinit_footbridge(struct devinit *d
414              0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);              0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);
415    
416          /*  The "fcom" console:  */          /*  The "fcom" console:  */
417          d->console_handle = console_start_slave(devinit->machine, "fcom");          d->console_handle = console_start_slave(devinit->machine, "fcom", 0);
418    
419          /*  A PCI bus:  */          /*  A PCI bus:  */
420          d->pcibus = bus_pci_init(          d->pcibus = bus_pci_init(
421                devinit->machine,
422              devinit->irq_nr,    /*  PCI controller irq  */              devinit->irq_nr,    /*  PCI controller irq  */
423              0x7c000000,         /*  PCI device io offset  */              0x7c000000,         /*  PCI device io offset  */
424              0x80000000,         /*  PCI device mem offset  */              0x80000000,         /*  PCI device mem offset  */
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