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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
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* |
* |
28 |
* $Id: dev_footbridge.c,v 1.36 2005/11/21 09:17:26 debug Exp $ |
* $Id: dev_footbridge.c,v 1.55 2007/02/03 16:18:56 debug Exp $ |
29 |
* |
* |
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* Footbridge. Used in Netwinder and Cats. |
* Footbridge. Used in Netwinder and Cats. |
31 |
* |
* |
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* TODO: |
* TODO: |
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* o) Add actual support for the fcom serial port. |
* o) Add actual support for the fcom serial port. |
34 |
* o) FIQs. |
* o) FIQs. |
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* o) Pretty much everything else as well :) (This entire thing |
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* is a quick hack to work primarily with NetBSD and OpenBSD |
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* as guest OSes.) |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
45 |
#include "console.h" |
#include "console.h" |
46 |
#include "cpu.h" |
#include "cpu.h" |
47 |
#include "device.h" |
#include "device.h" |
48 |
#include "devices.h" /* for struct footbridge_data */ |
#include "devices.h" |
49 |
#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "timer.h" |
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#include "dc21285reg.h" |
#include "dc21285reg.h" |
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#define DEV_FOOTBRIDGE_TICK_SHIFT 14 |
#define DEV_FOOTBRIDGE_TICK_SHIFT 14 |
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#define DEV_FOOTBRIDGE_LENGTH 0x400 |
#define DEV_FOOTBRIDGE_LENGTH 0x400 |
59 |
#define TIMER_POLL_THRESHOLD 15 |
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#define N_FOOTBRIDGE_TIMERS 4 |
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struct footbridge_data { |
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struct interrupt irq; |
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struct pci_data *pcibus; |
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int console_handle; |
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uint32_t timer_load[N_FOOTBRIDGE_TIMERS]; |
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uint32_t timer_value[N_FOOTBRIDGE_TIMERS]; |
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uint32_t timer_control[N_FOOTBRIDGE_TIMERS]; |
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struct interrupt timer_irq[N_FOOTBRIDGE_TIMERS]; |
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struct timer *timer[N_FOOTBRIDGE_TIMERS]; |
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int pending_timer_interrupts[N_FOOTBRIDGE_TIMERS]; |
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int irq_asserted; |
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uint32_t irq_status; |
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uint32_t irq_enable; |
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uint32_t fiq_status; |
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uint32_t fiq_enable; |
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}; |
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static void timer_tick0(struct timer *t, void *extra) |
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{ ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; } |
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static void timer_tick1(struct timer *t, void *extra) |
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{ ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; } |
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static void timer_tick2(struct timer *t, void *extra) |
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{ ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; } |
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static void timer_tick3(struct timer *t, void *extra) |
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{ ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; } |
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static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d, |
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int timer_nr) |
99 |
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{ |
100 |
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double freq = (double)cpu->machine->emulated_hz; |
101 |
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int cycles = d->timer_load[timer_nr]; |
102 |
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103 |
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if (d->timer_control[timer_nr] & TIMER_FCLK_16) |
104 |
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cycles <<= 4; |
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else if (d->timer_control[timer_nr] & TIMER_FCLK_256) |
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cycles <<= 8; |
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freq /= (double)cycles; |
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d->timer_value[timer_nr] = d->timer_load[timer_nr]; |
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/* printf("%i: %i -> %f Hz\n", timer_nr, |
112 |
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d->timer_load[timer_nr], freq); */ |
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114 |
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if (d->timer[timer_nr] == NULL) { |
115 |
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switch (timer_nr) { |
116 |
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case 0: d->timer[0] = timer_add(freq, timer_tick0, d); break; |
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case 1: d->timer[1] = timer_add(freq, timer_tick1, d); break; |
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case 2: d->timer[2] = timer_add(freq, timer_tick2, d); break; |
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case 3: d->timer[3] = timer_add(freq, timer_tick3, d); break; |
120 |
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} |
121 |
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} else { |
122 |
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timer_update_frequency(d->timer[timer_nr], freq); |
123 |
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} |
124 |
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} |
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127 |
/* |
/* |
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* dev_footbridge_tick(): |
* dev_footbridge_tick(): |
129 |
* |
* |
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* The 4 footbridge timers should decrease every now and then, and cause |
* The 4 footbridge timers should decrease and cause interrupts. Periodic |
131 |
* interrupts. Periodic interrupts restart as soon as they are acknowledged, |
* interrupts restart as soon as they are acknowledged, non-periodic |
132 |
* non-periodic interrupts need to be "reloaded" to restart. |
* interrupts need to be "reloaded" to restart. |
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* |
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* TODO: Hm. I thought I had solved this, but it didn't quite work. |
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* This needs to be re-checked against documentation, sometime. |
136 |
*/ |
*/ |
137 |
void dev_footbridge_tick(struct cpu *cpu, void *extra) |
void dev_footbridge_tick(struct cpu *cpu, void *extra) |
138 |
{ |
{ |
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int i; |
int i; |
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struct footbridge_data *d = (struct footbridge_data *) extra; |
struct footbridge_data *d = (struct footbridge_data *) extra; |
141 |
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if (!d->timer_being_read) |
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d->timer_poll_mode = 0; |
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for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
143 |
int amount = 1 << DEV_FOOTBRIDGE_TICK_SHIFT; |
if (d->timer_control[i] & TIMER_ENABLE) { |
144 |
if (d->timer_control[i] & TIMER_FCLK_16) |
if (d->pending_timer_interrupts[i] > 0) { |
145 |
amount >>= 4; |
d->timer_value[i] = random() % d->timer_load[i]; |
146 |
else if (d->timer_control[i] & TIMER_FCLK_256) |
INTERRUPT_ASSERT(d->timer_irq[i]); |
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amount >>= 8; |
} |
148 |
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} |
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} |
150 |
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} |
151 |
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if (d->timer_tick_countdown[i] == 0) |
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continue; |
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153 |
if (d->timer_value[i] > amount) |
/* |
154 |
d->timer_value[i] -= amount; |
* footbridge_interrupt_assert(): |
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else |
*/ |
156 |
d->timer_value[i] = 0; |
void footbridge_interrupt_assert(struct interrupt *interrupt) |
157 |
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{ |
158 |
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struct footbridge_data *d = (struct footbridge_data *) interrupt->extra; |
159 |
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d->irq_status |= interrupt->line; |
160 |
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161 |
if (d->timer_value[i] == 0) { |
if ((d->irq_status & d->irq_enable) && !d->irq_asserted) { |
162 |
d->timer_tick_countdown[i] --; |
d->irq_asserted = 1; |
163 |
if (d->timer_tick_countdown[i] > 0) |
INTERRUPT_ASSERT(d->irq); |
164 |
continue; |
} |
165 |
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} |
166 |
if (d->timer_control[i] & TIMER_ENABLE) |
|
167 |
cpu_interrupt(cpu, IRQ_TIMER_1 + i); |
|
168 |
d->timer_tick_countdown[i] = 0; |
/* |
169 |
} |
* footbridge_interrupt_deassert(): |
170 |
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*/ |
171 |
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void footbridge_interrupt_deassert(struct interrupt *interrupt) |
172 |
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{ |
173 |
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struct footbridge_data *d = (struct footbridge_data *) interrupt->extra; |
174 |
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d->irq_status &= ~interrupt->line; |
175 |
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176 |
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if (!(d->irq_status & d->irq_enable) && d->irq_asserted) { |
177 |
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d->irq_asserted = 0; |
178 |
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INTERRUPT_DEASSERT(d->irq); |
179 |
} |
} |
180 |
} |
} |
181 |
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* interrupt has occurred (and acknowledging it at the same time), than |
* interrupt has occurred (and acknowledging it at the same time), than |
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* dealing with the legacy 0x20/0xa0 ISA ports. |
* dealing with the legacy 0x20/0xa0 ISA ports. |
189 |
*/ |
*/ |
190 |
int dev_footbridge_isa_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(footbridge_isa) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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191 |
{ |
{ |
192 |
/* struct footbridge_data *d = extra; */ |
/* struct footbridge_data *d = extra; */ |
193 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
199 |
} |
} |
200 |
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201 |
x = cpu->machine->isa_pic_data.last_int; |
x = cpu->machine->isa_pic_data.last_int; |
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if (x == 0) |
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cpu_interrupt_ack(cpu, 32 + x); |
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if (x < 8) |
if (x < 8) |
203 |
odata = cpu->machine->isa_pic_data.pic1->irq_base + x; |
odata = cpu->machine->isa_pic_data.pic1->irq_base + x; |
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else |
else |
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213 |
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214 |
/* |
/* |
215 |
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* Reset pin at ISA port 0x338, at least in the NetWinder: |
216 |
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* |
217 |
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* TODO: NOT WORKING YET! |
218 |
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*/ |
219 |
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DEVICE_ACCESS(footbridge_reset) |
220 |
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{ |
221 |
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uint64_t idata = 0; |
222 |
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223 |
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if (writeflag == MEM_WRITE) { |
224 |
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idata = memory_readmax64(cpu, data, len); |
225 |
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if (idata & 0x40) { |
226 |
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debug("[ footbridge_reset: GP16: Halting. ]\n"); |
227 |
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cpu->running = 0; |
228 |
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exit(1); |
229 |
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} |
230 |
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} |
231 |
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return 1; |
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} |
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/* |
237 |
* dev_footbridge_pci_access(): |
* dev_footbridge_pci_access(): |
238 |
* |
* |
239 |
* The Footbridge PCI configuration space is not implemented as "address + |
* The Footbridge PCI configuration space is implemented as a direct memory |
240 |
* data port" pair, but instead a 24-bit (16 MB) chunk of physical memory |
* space (i.e. not one port for addr and one port for data). This function |
241 |
* decodes as the address. This function translates that into bus_pci_access |
* translates that into bus_pci calls. |
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* calls. |
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242 |
*/ |
*/ |
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int dev_footbridge_pci_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(footbridge_pci) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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244 |
{ |
{ |
245 |
struct footbridge_data *d = extra; |
struct footbridge_data *d = extra; |
246 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
247 |
int bus, device, function, regnr, res; |
int bus, dev, func, reg; |
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uint64_t pci_word; |
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248 |
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249 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
250 |
idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
251 |
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252 |
bus = (relative_addr >> 16) & 0xff; |
/* Decompose the (direct) address into its components: */ |
253 |
device = (relative_addr >> 11) & 0x1f; |
bus_pci_decompose_1(relative_addr, &bus, &dev, &func, ®); |
254 |
function = (relative_addr >> 8) & 0x7; |
bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg); |
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regnr = relative_addr & 0xff; |
|
255 |
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256 |
if (bus == 255) { |
if (bus == 255) { |
257 |
fatal("[ footbridge DEBUG ERROR: bus 255 unlikely," |
fatal("[ footbridge DEBUG ERROR: bus 255 unlikely," |
259 |
exit(1); |
exit(1); |
260 |
} |
} |
261 |
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262 |
debug("[ footbridge_pci: %s bus %i, device %i, function " |
debug("[ footbridge pci: %s bus %i, device %i, function %i, register " |
263 |
"%i, register %i ]\n", writeflag == MEM_READ? "read from" |
"%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus, |
264 |
: "write to", bus, device, function, regnr); |
dev, func, reg); |
265 |
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|
266 |
if (d->pcibus == NULL) { |
bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ? |
267 |
fatal("dev_footbridge_pci_access(): no PCI bus?\n"); |
&odata : &idata, len, writeflag); |
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return 0; |
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} |
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pci_word = relative_addr & 0x00ffffff; |
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res = bus_pci_access(cpu, mem, BUS_PCI_ADDR, |
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&pci_word, sizeof(uint32_t), MEM_WRITE, d->pcibus); |
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if (writeflag == MEM_READ) { |
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res = bus_pci_access(cpu, mem, BUS_PCI_DATA, |
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&pci_word, len, MEM_READ, d->pcibus); |
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odata = pci_word; |
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} else { |
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pci_word = idata; |
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res = bus_pci_access(cpu, mem, BUS_PCI_DATA, |
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&pci_word, len, MEM_WRITE, d->pcibus); |
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} |
|
268 |
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|
269 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
270 |
memory_writemax64(cpu, data, len, odata); |
memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
271 |
|
|
272 |
return 1; |
return 1; |
273 |
} |
} |
278 |
* |
* |
279 |
* The DC21285 registers. |
* The DC21285 registers. |
280 |
*/ |
*/ |
281 |
int dev_footbridge_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(footbridge) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
|
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int writeflag, void *extra) |
|
282 |
{ |
{ |
283 |
struct footbridge_data *d = extra; |
struct footbridge_data *d = extra; |
284 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
321 |
"EXTENSION: 0x%llx ]\n", (long long)idata); |
"EXTENSION: 0x%llx ]\n", (long long)idata); |
322 |
break; |
break; |
323 |
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|
324 |
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case SA_CONTROL: |
325 |
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/* Read by Linux: */ |
326 |
|
odata = PCI_CENTRAL_FUNCTION; |
327 |
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break; |
328 |
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|
329 |
case UART_DATA: |
case UART_DATA: |
330 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
331 |
console_putchar(d->console_handle, idata); |
console_putchar(d->console_handle, idata); |
361 |
case IRQ_ENABLE_SET: |
case IRQ_ENABLE_SET: |
362 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
363 |
d->irq_enable |= idata; |
d->irq_enable |= idata; |
364 |
cpu_interrupt(cpu, 64); |
if (d->irq_status & d->irq_enable) |
365 |
|
INTERRUPT_ASSERT(d->irq); |
366 |
|
else |
367 |
|
INTERRUPT_DEASSERT(d->irq); |
368 |
} else { |
} else { |
369 |
odata = d->irq_enable; |
odata = d->irq_enable; |
370 |
fatal("[ WARNING: footbridge read from " |
fatal("[ WARNING: footbridge read from " |
376 |
case IRQ_ENABLE_CLEAR: |
case IRQ_ENABLE_CLEAR: |
377 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
378 |
d->irq_enable &= ~idata; |
d->irq_enable &= ~idata; |
379 |
cpu_interrupt(cpu, 64); |
if (d->irq_status & d->irq_enable) |
380 |
|
INTERRUPT_ASSERT(d->irq); |
381 |
|
else |
382 |
|
INTERRUPT_DEASSERT(d->irq); |
383 |
} else { |
} else { |
384 |
odata = d->irq_enable; |
odata = d->irq_enable; |
385 |
fatal("[ WARNING: footbridge read from " |
fatal("[ WARNING: footbridge read from " |
420 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
421 |
odata = d->timer_load[timer_nr]; |
odata = d->timer_load[timer_nr]; |
422 |
else { |
else { |
423 |
d->timer_value[timer_nr] = |
d->timer_load[timer_nr] = idata & TIMER_MAX_VAL; |
424 |
d->timer_load[timer_nr] = idata & TIMER_MAX_VAL; |
reload_timer_value(cpu, d, timer_nr); |
425 |
debug("[ footbridge: timer %i (1-based), value %i ]\n", |
/* debug("[ footbridge: timer %i (1-based), " |
426 |
timer_nr + 1, (int)d->timer_value[timer_nr]); |
"value %i ]\n", timer_nr + 1, |
427 |
d->timer_tick_countdown[timer_nr] = 1; |
(int)d->timer_value[timer_nr]); */ |
428 |
cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]); |
429 |
} |
} |
430 |
break; |
break; |
431 |
|
|
432 |
case TIMER_1_VALUE: |
case TIMER_1_VALUE: |
433 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) |
|
/* |
|
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* NOTE/TODO: This is INCORRECT but speeds up NetBSD |
|
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* and OpenBSD boot sequences: if the timer is polled |
|
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* "very often" (such as during bootup), then this |
|
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* causes the timers to expire quickly. |
|
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*/ |
|
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d->timer_being_read = 1; |
|
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d->timer_poll_mode ++; |
|
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if (d->timer_poll_mode >= TIMER_POLL_THRESHOLD) { |
|
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d->timer_poll_mode = TIMER_POLL_THRESHOLD; |
|
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dev_footbridge_tick(cpu, d); |
|
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dev_footbridge_tick(cpu, d); |
|
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dev_footbridge_tick(cpu, d); |
|
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} |
|
434 |
odata = d->timer_value[timer_nr]; |
odata = d->timer_value[timer_nr]; |
435 |
d->timer_being_read = 0; |
else |
|
} else |
|
436 |
d->timer_value[timer_nr] = idata & TIMER_MAX_VAL; |
d->timer_value[timer_nr] = idata & TIMER_MAX_VAL; |
437 |
break; |
break; |
438 |
|
|
448 |
exit(1); |
exit(1); |
449 |
} |
} |
450 |
if (idata & TIMER_ENABLE) { |
if (idata & TIMER_ENABLE) { |
451 |
d->timer_value[timer_nr] = |
reload_timer_value(cpu, d, timer_nr); |
452 |
d->timer_load[timer_nr]; |
} else { |
453 |
d->timer_tick_countdown[timer_nr] = 1; |
d->pending_timer_interrupts[timer_nr] = 0; |
454 |
} |
} |
455 |
cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]); |
456 |
} |
} |
457 |
break; |
break; |
458 |
|
|
459 |
case TIMER_1_CLEAR: |
case TIMER_1_CLEAR: |
460 |
if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) { |
if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) { |
461 |
d->timer_value[timer_nr] = d->timer_load[timer_nr]; |
reload_timer_value(cpu, d, timer_nr); |
462 |
d->timer_tick_countdown[timer_nr] = 1; |
} |
463 |
|
|
464 |
|
if (d->pending_timer_interrupts[timer_nr] > 0) { |
465 |
|
d->pending_timer_interrupts[timer_nr] --; |
466 |
} |
} |
467 |
cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
|
468 |
|
INTERRUPT_DEASSERT(d->timer_irq[timer_nr]); |
469 |
break; |
break; |
470 |
|
|
471 |
default:if (writeflag == MEM_READ) { |
default:if (writeflag == MEM_READ) { |
484 |
} |
} |
485 |
|
|
486 |
|
|
487 |
/* |
DEVINIT(footbridge) |
|
* devinit_footbridge(): |
|
|
*/ |
|
|
int devinit_footbridge(struct devinit *devinit) |
|
488 |
{ |
{ |
489 |
struct footbridge_data *d; |
struct footbridge_data *d; |
490 |
|
char irq_path[300], irq_path_isa[300]; |
491 |
uint64_t pci_addr = 0x7b000000; |
uint64_t pci_addr = 0x7b000000; |
492 |
int i; |
int i; |
493 |
|
|
498 |
} |
} |
499 |
memset(d, 0, sizeof(struct footbridge_data)); |
memset(d, 0, sizeof(struct footbridge_data)); |
500 |
|
|
501 |
|
/* Connect to the CPU which this footbridge will interrupt: */ |
502 |
|
INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
503 |
|
|
504 |
/* DC21285 register access: */ |
/* DC21285 register access: */ |
505 |
memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
506 |
devinit->addr, DEV_FOOTBRIDGE_LENGTH, |
devinit->addr, DEV_FOOTBRIDGE_LENGTH, |
511 |
0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL); |
0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL); |
512 |
|
|
513 |
/* The "fcom" console: */ |
/* The "fcom" console: */ |
514 |
d->console_handle = console_start_slave(devinit->machine, "fcom"); |
d->console_handle = console_start_slave(devinit->machine, "fcom", 0); |
515 |
|
|
516 |
|
/* Register 32 footbridge interrupts: */ |
517 |
|
snprintf(irq_path, sizeof(irq_path), "%s.footbridge", |
518 |
|
devinit->interrupt_path); |
519 |
|
for (i=0; i<32; i++) { |
520 |
|
struct interrupt interrupt_template; |
521 |
|
char tmpstr[200]; |
522 |
|
|
523 |
|
memset(&interrupt_template, 0, sizeof(interrupt_template)); |
524 |
|
interrupt_template.line = 1 << i; |
525 |
|
snprintf(tmpstr, sizeof(tmpstr), "%s.%i", irq_path, i); |
526 |
|
interrupt_template.name = tmpstr; |
527 |
|
|
528 |
|
interrupt_template.extra = d; |
529 |
|
interrupt_template.interrupt_assert = |
530 |
|
footbridge_interrupt_assert; |
531 |
|
interrupt_template.interrupt_deassert = |
532 |
|
footbridge_interrupt_deassert; |
533 |
|
interrupt_handler_register(&interrupt_template); |
534 |
|
|
535 |
|
/* Connect locally to some interrupts: */ |
536 |
|
if (i>=IRQ_TIMER_1 && i<=IRQ_TIMER_4) |
537 |
|
INTERRUPT_CONNECT(tmpstr, d->timer_irq[i-IRQ_TIMER_1]); |
538 |
|
} |
539 |
|
|
540 |
|
switch (devinit->machine->machine_type) { |
541 |
|
case MACHINE_CATS: |
542 |
|
snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.10", irq_path); |
543 |
|
break; |
544 |
|
case MACHINE_NETWINDER: |
545 |
|
snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.11", irq_path); |
546 |
|
break; |
547 |
|
default:fatal("footbridge unimpl machine type\n"); |
548 |
|
exit(1); |
549 |
|
} |
550 |
|
|
551 |
/* A PCI bus: */ |
/* A PCI bus: */ |
552 |
d->pcibus = bus_pci_init( |
d->pcibus = bus_pci_init( |
553 |
devinit->irq_nr, /* PCI controller irq */ |
devinit->machine, |
554 |
|
irq_path, |
555 |
0x7c000000, /* PCI device io offset */ |
0x7c000000, /* PCI device io offset */ |
556 |
0x80000000, /* PCI device mem offset */ |
0x80000000, /* PCI device mem offset */ |
557 |
0x00000000, /* PCI port base */ |
0x00000000, /* PCI port base */ |
558 |
0x00000000, /* PCI mem base */ |
0x00000000, /* PCI mem base */ |
559 |
0, /* PCI irq base: TODO */ |
irq_path, /* PCI irq base */ |
560 |
0x7c000000, /* ISA port base */ |
0x7c000000, /* ISA port base */ |
561 |
0x80000000, /* ISA mem base */ |
0x80000000, /* ISA mem base */ |
562 |
32); /* ISA port base */ |
irq_path_isa); /* ISA port base */ |
563 |
|
|
564 |
/* ... with some default devices for known machine types: */ |
/* ... with some default devices for known machine types: */ |
565 |
switch (devinit->machine->machine_type) { |
switch (devinit->machine->machine_type) { |
576 |
devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553"); |
devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553"); |
577 |
bus_pci_add(devinit->machine, d->pcibus, |
bus_pci_add(devinit->machine, d->pcibus, |
578 |
devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105"); |
devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105"); |
579 |
|
memory_device_register(devinit->machine->memory, |
580 |
|
"footbridge_reset", 0x7c000338, 1, |
581 |
|
dev_footbridge_reset_access, d, DM_DEFAULT, NULL); |
582 |
break; |
break; |
583 |
default:fatal("footbridge: unimplemented machine type.\n"); |
default:fatal("footbridge: unimplemented machine type.\n"); |
584 |
exit(1); |
exit(1); |
595 |
d->timer_load[i] = TIMER_MAX_VAL; |
d->timer_load[i] = TIMER_MAX_VAL; |
596 |
} |
} |
597 |
machine_add_tickfunction(devinit->machine, |
machine_add_tickfunction(devinit->machine, |
598 |
dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT); |
dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT, 0.0); |
599 |
|
|
600 |
devinit->return_ptr = d; |
devinit->return_ptr = d->pcibus; |
601 |
return 1; |
return 1; |
602 |
} |
} |
603 |
|
|