/[gxemul]/trunk/src/devices/dev_footbridge.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC revision 42 by dpavlin, Mon Oct 8 16:22:32 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: dev_footbridge.c,v 1.43 2006/03/04 12:38:47 debug Exp $   *  $Id: dev_footbridge.c,v 1.57 2007/06/15 19:11:15 debug Exp $
29   *   *
30   *  Footbridge. Used in Netwinder and Cats.   *  COMMENT: DC21285 "Footbridge" controller; used in Netwinder and Cats
31   *   *
32   *  TODO:   *  TODO:
33   *      o)  Add actual support for the fcom serial port.   *      o)  Add actual support for the fcom serial port.
34   *      o)  FIQs.   *      o)  FIQs.
35   *      o)  Pretty much everything else as well :)  (This entire thing   *      o)  Pretty much everything else as well :)  (This entire thing
36   *          is a quick hack to work primarily with NetBSD and OpenBSD   *          is a quick hack to work primarily with NetBSD and OpenBSD
37   *          as a guest OS.)   *          as guest OSes.)
38   */   */
39    
40  #include <stdio.h>  #include <stdio.h>
# Line 49  Line 49 
49  #include "machine.h"  #include "machine.h"
50  #include "memory.h"  #include "memory.h"
51  #include "misc.h"  #include "misc.h"
52    #include "timer.h"
53    
54    
55  #include "dc21285reg.h"  #include "dc21285reg.h"
56    
57  #define DEV_FOOTBRIDGE_TICK_SHIFT       14  #define DEV_FOOTBRIDGE_TICK_SHIFT       14
58  #define DEV_FOOTBRIDGE_LENGTH           0x400  #define DEV_FOOTBRIDGE_LENGTH           0x400
59  #define TIMER_POLL_THRESHOLD            15  
60    #define N_FOOTBRIDGE_TIMERS             4
61    
62    struct footbridge_data {
63            struct interrupt irq;
64    
65            struct pci_data *pcibus;
66    
67            int             console_handle;
68    
69            uint32_t        timer_load[N_FOOTBRIDGE_TIMERS];
70            uint32_t        timer_value[N_FOOTBRIDGE_TIMERS];
71            uint32_t        timer_control[N_FOOTBRIDGE_TIMERS];
72    
73            struct interrupt timer_irq[N_FOOTBRIDGE_TIMERS];
74            struct timer    *timer[N_FOOTBRIDGE_TIMERS];
75            int             pending_timer_interrupts[N_FOOTBRIDGE_TIMERS];
76    
77            int             irq_asserted;
78    
79            uint32_t        irq_status;
80            uint32_t        irq_enable;
81    
82            uint32_t        fiq_status;
83            uint32_t        fiq_enable;
84    };
85    
86    
87    static void timer_tick0(struct timer *t, void *extra)
88    { ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; }
89    static void timer_tick1(struct timer *t, void *extra)
90    { ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; }
91    static void timer_tick2(struct timer *t, void *extra)
92    { ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; }
93    static void timer_tick3(struct timer *t, void *extra)
94    { ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; }
95    
96    
97    static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d,
98            int timer_nr)
99    {
100            double freq = (double)cpu->machine->emulated_hz;
101            int cycles = d->timer_load[timer_nr];
102    
103            if (d->timer_control[timer_nr] & TIMER_FCLK_16)
104                    cycles <<= 4;
105            else if (d->timer_control[timer_nr] & TIMER_FCLK_256)
106                    cycles <<= 8;
107            freq /= (double)cycles;
108    
109            d->timer_value[timer_nr] = d->timer_load[timer_nr];
110    
111            /*  printf("%i: %i -> %f Hz\n", timer_nr,
112                d->timer_load[timer_nr], freq);  */
113    
114            if (d->timer[timer_nr] == NULL) {
115                    switch (timer_nr) {
116                    case 0: d->timer[0] = timer_add(freq, timer_tick0, d); break;
117                    case 1: d->timer[1] = timer_add(freq, timer_tick1, d); break;
118                    case 2: d->timer[2] = timer_add(freq, timer_tick2, d); break;
119                    case 3: d->timer[3] = timer_add(freq, timer_tick3, d); break;
120                    }
121            } else {
122                    timer_update_frequency(d->timer[timer_nr], freq);
123            }
124    }
125    
126    
127  /*  /*
128   *  dev_footbridge_tick():   *  The 4 footbridge timers should decrease and cause interrupts. Periodic
129     *  interrupts restart as soon as they are acknowledged, non-periodic
130     *  interrupts need to be "reloaded" to restart.
131   *   *
132   *  The 4 footbridge timers should decrease every now and then, and cause   *  TODO: Hm. I thought I had solved this, but it didn't quite work.
133   *  interrupts. Periodic interrupts restart as soon as they are acknowledged,   *        This needs to be re-checked against documentation, sometime.
  *  non-periodic interrupts need to be "reloaded" to restart.  
134   */   */
135  void dev_footbridge_tick(struct cpu *cpu, void *extra)  DEVICE_TICK(footbridge)
136  {  {
137            struct footbridge_data *d = extra;
138          int i;          int i;
         struct footbridge_data *d = (struct footbridge_data *) extra;  
   
         if (!d->timer_being_read)  
                 d->timer_poll_mode = 0;  
139    
140          for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {          for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
141                  unsigned int amount = 1 << DEV_FOOTBRIDGE_TICK_SHIFT;                  if (d->timer_control[i] & TIMER_ENABLE) {
142                  if (d->timer_control[i] & TIMER_FCLK_16)                          if (d->pending_timer_interrupts[i] > 0) {
143                          amount >>= 4;                                  d->timer_value[i] = random() % d->timer_load[i];
144                  else if (d->timer_control[i] & TIMER_FCLK_256)                                  INTERRUPT_ASSERT(d->timer_irq[i]);
145                          amount >>= 8;                          }
146                    }
147            }
148    }
149    
                 if (d->timer_tick_countdown[i] == 0)  
                         continue;  
150    
151                  if (d->timer_value[i] > amount)  /*
152                          d->timer_value[i] -= amount;   *  footbridge_interrupt_assert():
153                  else   */
154                          d->timer_value[i] = 0;  void footbridge_interrupt_assert(struct interrupt *interrupt)
155    {
156            struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
157            d->irq_status |= interrupt->line;
158    
159                  if (d->timer_value[i] == 0) {          if ((d->irq_status & d->irq_enable) && !d->irq_asserted) {
160                          d->timer_tick_countdown[i] --;                  d->irq_asserted = 1;
161                          if (d->timer_tick_countdown[i] > 0)                  INTERRUPT_ASSERT(d->irq);
162                                  continue;          }
163    }
164                          if (d->timer_control[i] & TIMER_ENABLE)  
165                                  cpu_interrupt(cpu, IRQ_TIMER_1 + i);  
166                          d->timer_tick_countdown[i] = 0;  /*
167                  }   *  footbridge_interrupt_deassert():
168     */
169    void footbridge_interrupt_deassert(struct interrupt *interrupt)
170    {
171            struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
172            d->irq_status &= ~interrupt->line;
173    
174            if (!(d->irq_status & d->irq_enable) && d->irq_asserted) {
175                    d->irq_asserted = 0;
176                    INTERRUPT_DEASSERT(d->irq);
177          }          }
178  }  }
179    
180    
181  /*  /*
  *  dev_footbridge_isa_access():  
  *  
182   *  Reading the byte at 0x79000000 is a quicker way to figure out which ISA   *  Reading the byte at 0x79000000 is a quicker way to figure out which ISA
183   *  interrupt has occurred (and acknowledging it at the same time), than   *  interrupt has occurred (and acknowledging it at the same time), than
184   *  dealing with the legacy 0x20/0xa0 ISA ports.   *  dealing with the legacy 0x20/0xa0 ISA ports.
# Line 120  DEVICE_ACCESS(footbridge_isa) Line 195  DEVICE_ACCESS(footbridge_isa)
195          }          }
196    
197          x = cpu->machine->isa_pic_data.last_int;          x = cpu->machine->isa_pic_data.last_int;
         if (x == 0)  
                 cpu_interrupt_ack(cpu, 32 + x);  
   
198          if (x < 8)          if (x < 8)
199                  odata = cpu->machine->isa_pic_data.pic1->irq_base + x;                  odata = cpu->machine->isa_pic_data.pic1->irq_base + x;
200          else          else
# Line 136  DEVICE_ACCESS(footbridge_isa) Line 208  DEVICE_ACCESS(footbridge_isa)
208    
209    
210  /*  /*
211   *  dev_footbridge_pci_access():   *  Reset pin at ISA port 0x338, at least in the NetWinder:
212   *   *
213     *  TODO: NOT WORKING YET!
214     */
215    DEVICE_ACCESS(footbridge_reset)
216    {
217            uint64_t idata = 0;
218    
219            if (writeflag == MEM_WRITE) {
220                    idata = memory_readmax64(cpu, data, len);
221                    if (idata & 0x40) {
222                            debug("[ footbridge_reset: GP16: Halting. ]\n");
223                            cpu->running = 0;
224    exit(1);
225                    }
226            }
227    
228            return 1;
229    }
230    
231    
232    /*
233   *  The Footbridge PCI configuration space is implemented as a direct memory   *  The Footbridge PCI configuration space is implemented as a direct memory
234   *  space (i.e. not one port for addr and one port for data). This function   *  space (i.e. not one port for addr and one port for data). This function
235   *  translates that into bus_pci calls.   *  translates that into bus_pci calls.
# Line 175  DEVICE_ACCESS(footbridge_pci) Line 267  DEVICE_ACCESS(footbridge_pci)
267  }  }
268    
269    
 /*  
  *  dev_footbridge_access():  
  *  
  *  The DC21285 registers.  
  */  
270  DEVICE_ACCESS(footbridge)  DEVICE_ACCESS(footbridge)
271  {  {
272          struct footbridge_data *d = extra;          struct footbridge_data *d = extra;
# Line 263  DEVICE_ACCESS(footbridge) Line 350  DEVICE_ACCESS(footbridge)
350          case IRQ_ENABLE_SET:          case IRQ_ENABLE_SET:
351                  if (writeflag == MEM_WRITE) {                  if (writeflag == MEM_WRITE) {
352                          d->irq_enable |= idata;                          d->irq_enable |= idata;
353                          cpu_interrupt(cpu, 64);                          if (d->irq_status & d->irq_enable)
354                                    INTERRUPT_ASSERT(d->irq);
355                            else
356                                    INTERRUPT_DEASSERT(d->irq);
357                  } else {                  } else {
358                          odata = d->irq_enable;                          odata = d->irq_enable;
359                          fatal("[ WARNING: footbridge read from "                          fatal("[ WARNING: footbridge read from "
# Line 275  DEVICE_ACCESS(footbridge) Line 365  DEVICE_ACCESS(footbridge)
365          case IRQ_ENABLE_CLEAR:          case IRQ_ENABLE_CLEAR:
366                  if (writeflag == MEM_WRITE) {                  if (writeflag == MEM_WRITE) {
367                          d->irq_enable &= ~idata;                          d->irq_enable &= ~idata;
368                          cpu_interrupt(cpu, 64);                          if (d->irq_status & d->irq_enable)
369                                    INTERRUPT_ASSERT(d->irq);
370                            else
371                                    INTERRUPT_DEASSERT(d->irq);
372                  } else {                  } else {
373                          odata = d->irq_enable;                          odata = d->irq_enable;
374                          fatal("[ WARNING: footbridge read from "                          fatal("[ WARNING: footbridge read from "
# Line 316  DEVICE_ACCESS(footbridge) Line 409  DEVICE_ACCESS(footbridge)
409                  if (writeflag == MEM_READ)                  if (writeflag == MEM_READ)
410                          odata = d->timer_load[timer_nr];                          odata = d->timer_load[timer_nr];
411                  else {                  else {
412                          d->timer_value[timer_nr] =                          d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;
413                              d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;                          reload_timer_value(cpu, d, timer_nr);
414                          debug("[ footbridge: timer %i (1-based), value %i ]\n",                          /*  debug("[ footbridge: timer %i (1-based), "
415                              timer_nr + 1, (int)d->timer_value[timer_nr]);                              "value %i ]\n", timer_nr + 1,
416                          d->timer_tick_countdown[timer_nr] = 1;                              (int)d->timer_value[timer_nr]);  */
417                          cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);                          INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
418                  }                  }
419                  break;                  break;
420    
421          case TIMER_1_VALUE:          case TIMER_1_VALUE:
422                  if (writeflag == MEM_READ) {                  if (writeflag == MEM_READ)
                         /*  
                          *  NOTE/TODO: This is INCORRECT but speeds up NetBSD  
                          *  and OpenBSD boot sequences: if the timer is polled  
                          *  "very often" (such as during bootup), then this  
                          *  causes the timers to expire quickly.  
                          */  
                         d->timer_being_read = 1;  
                         d->timer_poll_mode ++;  
                         if (d->timer_poll_mode >= TIMER_POLL_THRESHOLD) {  
                                 d->timer_poll_mode = TIMER_POLL_THRESHOLD;  
                                 dev_footbridge_tick(cpu, d);  
                                 dev_footbridge_tick(cpu, d);  
                                 dev_footbridge_tick(cpu, d);  
                         }  
423                          odata = d->timer_value[timer_nr];                          odata = d->timer_value[timer_nr];
424                          d->timer_being_read = 0;                  else
                 } else  
425                          d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;                          d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;
426                  break;                  break;
427    
# Line 359  DEVICE_ACCESS(footbridge) Line 437  DEVICE_ACCESS(footbridge)
437                                  exit(1);                                  exit(1);
438                          }                          }
439                          if (idata & TIMER_ENABLE) {                          if (idata & TIMER_ENABLE) {
440                                  d->timer_value[timer_nr] =                                  reload_timer_value(cpu, d, timer_nr);
441                                      d->timer_load[timer_nr];                          } else {
442                                  d->timer_tick_countdown[timer_nr] = 1;                                  d->pending_timer_interrupts[timer_nr] = 0;
443                          }                          }
444                          cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);                          INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
445                  }                  }
446                  break;                  break;
447    
448          case TIMER_1_CLEAR:          case TIMER_1_CLEAR:
449                  if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {                  if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {
450                          d->timer_value[timer_nr] = d->timer_load[timer_nr];                          reload_timer_value(cpu, d, timer_nr);
451                          d->timer_tick_countdown[timer_nr] = 1;                  }
452    
453                    if (d->pending_timer_interrupts[timer_nr] > 0) {
454                            d->pending_timer_interrupts[timer_nr] --;
455                  }                  }
456                  cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);  
457                    INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
458                  break;                  break;
459    
460          default:if (writeflag == MEM_READ) {          default:if (writeflag == MEM_READ) {
# Line 394  DEVICE_ACCESS(footbridge) Line 476  DEVICE_ACCESS(footbridge)
476  DEVINIT(footbridge)  DEVINIT(footbridge)
477  {  {
478          struct footbridge_data *d;          struct footbridge_data *d;
479            char irq_path[300], irq_path_isa[300];
480          uint64_t pci_addr = 0x7b000000;          uint64_t pci_addr = 0x7b000000;
481          int i;          int i;
482    
483          d = malloc(sizeof(struct footbridge_data));          CHECK_ALLOCATION(d = malloc(sizeof(struct footbridge_data)));
         if (d == NULL) {  
                 fprintf(stderr, "out of memory\n");  
                 exit(1);  
         }  
484          memset(d, 0, sizeof(struct footbridge_data));          memset(d, 0, sizeof(struct footbridge_data));
485    
486            /*  Connect to the CPU which this footbridge will interrupt:  */
487            INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
488    
489          /*  DC21285 register access:  */          /*  DC21285 register access:  */
490          memory_device_register(devinit->machine->memory, devinit->name,          memory_device_register(devinit->machine->memory, devinit->name,
491              devinit->addr, DEV_FOOTBRIDGE_LENGTH,              devinit->addr, DEV_FOOTBRIDGE_LENGTH,
# Line 416  DEVINIT(footbridge) Line 498  DEVINIT(footbridge)
498          /*  The "fcom" console:  */          /*  The "fcom" console:  */
499          d->console_handle = console_start_slave(devinit->machine, "fcom", 0);          d->console_handle = console_start_slave(devinit->machine, "fcom", 0);
500    
501            /*  Register 32 footbridge interrupts:  */
502            snprintf(irq_path, sizeof(irq_path), "%s.footbridge",
503                devinit->interrupt_path);
504            for (i=0; i<32; i++) {
505                    struct interrupt interrupt_template;
506                    char tmpstr[200];
507    
508                    memset(&interrupt_template, 0, sizeof(interrupt_template));
509                    interrupt_template.line = 1 << i;
510                    snprintf(tmpstr, sizeof(tmpstr), "%s.%i", irq_path, i);
511                    interrupt_template.name = tmpstr;
512    
513                    interrupt_template.extra = d;
514                    interrupt_template.interrupt_assert =
515                        footbridge_interrupt_assert;
516                    interrupt_template.interrupt_deassert =
517                        footbridge_interrupt_deassert;
518                    interrupt_handler_register(&interrupt_template);
519    
520                    /*  Connect locally to some interrupts:  */
521                    if (i>=IRQ_TIMER_1 && i<=IRQ_TIMER_4)
522                            INTERRUPT_CONNECT(tmpstr, d->timer_irq[i-IRQ_TIMER_1]);
523            }
524    
525            switch (devinit->machine->machine_type) {
526            case MACHINE_CATS:
527                    snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.10", irq_path);
528                    break;
529            case MACHINE_NETWINDER:
530                    snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.11", irq_path);
531                    break;
532            default:fatal("footbridge unimpl machine type\n");
533                    exit(1);
534            }
535    
536          /*  A PCI bus:  */          /*  A PCI bus:  */
537          d->pcibus = bus_pci_init(          d->pcibus = bus_pci_init(
538              devinit->machine,              devinit->machine,
539              devinit->irq_nr,    /*  PCI controller irq  */              irq_path,
540              0x7c000000,         /*  PCI device io offset  */              0x7c000000,         /*  PCI device io offset  */
541              0x80000000,         /*  PCI device mem offset  */              0x80000000,         /*  PCI device mem offset  */
542              0x00000000,         /*  PCI port base  */              0x00000000,         /*  PCI port base  */
543              0x00000000,         /*  PCI mem base  */              0x00000000,         /*  PCI mem base  */
544              0,                  /*  PCI irq base: TODO  */              irq_path,           /*  PCI irq base  */
545              0x7c000000,         /*  ISA port base  */              0x7c000000,         /*  ISA port base  */
546              0x80000000,         /*  ISA mem base  */              0x80000000,         /*  ISA mem base  */
547              32);                /*  ISA port base  */              irq_path_isa);      /*  ISA port base  */
548    
549          /*  ... with some default devices for known machine types:  */          /*  ... with some default devices for known machine types:  */
550          switch (devinit->machine->machine_type) {          switch (devinit->machine->machine_type) {
# Line 444  DEVINIT(footbridge) Line 561  DEVINIT(footbridge)
561                      devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");                      devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");
562                  bus_pci_add(devinit->machine, d->pcibus,                  bus_pci_add(devinit->machine, d->pcibus,
563                      devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");                      devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");
564                    memory_device_register(devinit->machine->memory,
565                        "footbridge_reset", 0x7c000338, 1,
566                        dev_footbridge_reset_access, d, DM_DEFAULT, NULL);
567                  break;                  break;
568          default:fatal("footbridge: unimplemented machine type.\n");          default:fatal("footbridge: unimplemented machine type.\n");
569                  exit(1);                  exit(1);
# Line 459  DEVINIT(footbridge) Line 579  DEVINIT(footbridge)
579                  d->timer_control[i] = TIMER_MODE_PERIODIC;                  d->timer_control[i] = TIMER_MODE_PERIODIC;
580                  d->timer_load[i] = TIMER_MAX_VAL;                  d->timer_load[i] = TIMER_MAX_VAL;
581          }          }
582    
583          machine_add_tickfunction(devinit->machine,          machine_add_tickfunction(devinit->machine,
584              dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT, 0.0);              dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT);
585    
586          devinit->return_ptr = d;          devinit->return_ptr = d->pcibus;
587          return 1;          return 1;
588  }  }
589    
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