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dpavlin |
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/* |
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dpavlin |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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dpavlin |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: dev_footbridge.c,v 1.44 2006/08/11 17:43:30 debug Exp $ |
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dpavlin |
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* |
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* Footbridge. Used in Netwinder and Cats. |
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* |
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dpavlin |
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* TODO: |
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dpavlin |
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* o) Add actual support for the fcom serial port. |
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* o) FIQs. |
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dpavlin |
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* o) Pretty much everything else as well :) (This entire thing |
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* is a quick hack to work primarily with NetBSD and OpenBSD |
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* as a guest OS.) |
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dpavlin |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "bus_pci.h" |
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#include "console.h" |
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#include "cpu.h" |
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#include "device.h" |
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dpavlin |
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#include "devices.h" |
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dpavlin |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "dc21285reg.h" |
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#define DEV_FOOTBRIDGE_TICK_SHIFT 14 |
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#define DEV_FOOTBRIDGE_LENGTH 0x400 |
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dpavlin |
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#define TIMER_POLL_THRESHOLD 15 |
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dpavlin |
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|
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/* |
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* dev_footbridge_tick(): |
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* |
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* The 4 footbridge timers should decrease every now and then, and cause |
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* interrupts. Periodic interrupts restart as soon as they are acknowledged, |
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* non-periodic interrupts need to be "reloaded" to restart. |
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*/ |
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void dev_footbridge_tick(struct cpu *cpu, void *extra) |
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{ |
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int i; |
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struct footbridge_data *d = (struct footbridge_data *) extra; |
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dpavlin |
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if (!d->timer_being_read) |
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d->timer_poll_mode = 0; |
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dpavlin |
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for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
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dpavlin |
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unsigned int amount = 1 << DEV_FOOTBRIDGE_TICK_SHIFT; |
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dpavlin |
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if (d->timer_control[i] & TIMER_FCLK_16) |
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amount >>= 4; |
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else if (d->timer_control[i] & TIMER_FCLK_256) |
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amount >>= 8; |
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if (d->timer_tick_countdown[i] == 0) |
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continue; |
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if (d->timer_value[i] > amount) |
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d->timer_value[i] -= amount; |
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else |
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d->timer_value[i] = 0; |
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if (d->timer_value[i] == 0) { |
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d->timer_tick_countdown[i] --; |
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if (d->timer_tick_countdown[i] > 0) |
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continue; |
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if (d->timer_control[i] & TIMER_ENABLE) |
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cpu_interrupt(cpu, IRQ_TIMER_1 + i); |
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d->timer_tick_countdown[i] = 0; |
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} |
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} |
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} |
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/* |
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* dev_footbridge_isa_access(): |
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* |
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dpavlin |
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* Reading the byte at 0x79000000 is a quicker way to figure out which ISA |
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* interrupt has occurred (and acknowledging it at the same time), than |
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* dealing with the legacy 0x20/0xa0 ISA ports. |
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dpavlin |
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*/ |
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DEVICE_ACCESS(footbridge_isa) |
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dpavlin |
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{ |
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/* struct footbridge_data *d = extra; */ |
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uint64_t idata = 0, odata = 0; |
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int x; |
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dpavlin |
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if (writeflag == MEM_WRITE) { |
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idata = memory_readmax64(cpu, data, len); |
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dpavlin |
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fatal("[ footbridge_isa: WARNING/TODO: write! ]\n"); |
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dpavlin |
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} |
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dpavlin |
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|
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dpavlin |
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x = cpu->machine->isa_pic_data.last_int; |
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if (x == 0) |
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cpu_interrupt_ack(cpu, 32 + x); |
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dpavlin |
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dpavlin |
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if (x < 8) |
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odata = cpu->machine->isa_pic_data.pic1->irq_base + x; |
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else |
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odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8; |
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dpavlin |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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/* |
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dpavlin |
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* Reset pin at ISA port 0x338, at least in the NetWinder: |
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* |
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* TODO: NOT WORKING YET! |
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*/ |
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DEVICE_ACCESS(footbridge_reset) |
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{ |
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uint64_t idata = 0; |
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if (writeflag == MEM_WRITE) { |
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idata = memory_readmax64(cpu, data, len); |
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if (idata & 0x40) { |
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debug("[ footbridge_reset: GP16: Halting. ]\n"); |
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cpu->running = 0; |
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exit(1); |
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} |
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} |
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return 1; |
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} |
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/* |
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dpavlin |
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* dev_footbridge_pci_access(): |
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* |
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dpavlin |
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* The Footbridge PCI configuration space is implemented as a direct memory |
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* space (i.e. not one port for addr and one port for data). This function |
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* translates that into bus_pci calls. |
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dpavlin |
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*/ |
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dpavlin |
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DEVICE_ACCESS(footbridge_pci) |
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dpavlin |
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{ |
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struct footbridge_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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dpavlin |
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int bus, dev, func, reg; |
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dpavlin |
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|
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dpavlin |
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if (writeflag == MEM_WRITE) |
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dpavlin |
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idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
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dpavlin |
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|
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dpavlin |
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/* Decompose the (direct) address into its components: */ |
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bus_pci_decompose_1(relative_addr, &bus, &dev, &func, ®); |
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bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg); |
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dpavlin |
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if (bus == 255) { |
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fatal("[ footbridge DEBUG ERROR: bus 255 unlikely," |
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" pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc); |
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exit(1); |
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} |
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dpavlin |
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debug("[ footbridge pci: %s bus %i, device %i, function %i, register " |
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"%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus, |
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dev, func, reg); |
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dpavlin |
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dpavlin |
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bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ? |
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&odata : &idata, len, writeflag); |
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dpavlin |
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if (writeflag == MEM_READ) |
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dpavlin |
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memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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dpavlin |
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return 1; |
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} |
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/* |
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* dev_footbridge_access(): |
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* |
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* The DC21285 registers. |
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*/ |
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dpavlin |
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DEVICE_ACCESS(footbridge) |
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dpavlin |
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{ |
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struct footbridge_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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int timer_nr = 0; |
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dpavlin |
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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dpavlin |
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if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) { |
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timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1); |
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relative_addr &= ~0x060; |
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} |
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switch (relative_addr) { |
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case VENDOR_ID: |
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odata = 0x1011; /* DC21285_VENDOR_ID */ |
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break; |
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case DEVICE_ID: |
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odata = 0x1065; /* DC21285_DEVICE_ID */ |
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break; |
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dpavlin |
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case 0x04: |
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case 0x0c: |
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case 0x10: |
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case 0x14: |
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case 0x18: |
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/* TODO. Written to by Linux. */ |
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break; |
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dpavlin |
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case REVISION: |
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odata = 3; /* footbridge revision number */ |
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break; |
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dpavlin |
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case PCI_ADDRESS_EXTENSION: |
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/* TODO: Written to by Linux. */ |
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if (writeflag == MEM_WRITE && idata != 0) |
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fatal("[ footbridge: TODO: write to PCI_ADDRESS_" |
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"EXTENSION: 0x%llx ]\n", (long long)idata); |
246 |
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break; |
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dpavlin |
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case SA_CONTROL: |
249 |
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/* Read by Linux: */ |
250 |
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odata = PCI_CENTRAL_FUNCTION; |
251 |
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break; |
252 |
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dpavlin |
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case UART_DATA: |
254 |
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if (writeflag == MEM_WRITE) |
255 |
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console_putchar(d->console_handle, idata); |
256 |
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break; |
257 |
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258 |
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case UART_RX_STAT: |
259 |
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/* TODO */ |
260 |
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odata = 0; |
261 |
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break; |
262 |
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263 |
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case UART_FLAGS: |
264 |
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odata = UART_TX_EMPTY; |
265 |
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break; |
266 |
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267 |
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case IRQ_STATUS: |
268 |
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if (writeflag == MEM_READ) |
269 |
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odata = d->irq_status & d->irq_enable; |
270 |
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else { |
271 |
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fatal("[ WARNING: footbridge write to irq status? ]\n"); |
272 |
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exit(1); |
273 |
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} |
274 |
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break; |
275 |
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276 |
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case IRQ_RAW_STATUS: |
277 |
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if (writeflag == MEM_READ) |
278 |
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odata = d->irq_status; |
279 |
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else { |
280 |
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fatal("[ footbridge write to irq_raw_status ]\n"); |
281 |
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exit(1); |
282 |
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} |
283 |
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break; |
284 |
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285 |
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case IRQ_ENABLE_SET: |
286 |
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if (writeflag == MEM_WRITE) { |
287 |
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d->irq_enable |= idata; |
288 |
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cpu_interrupt(cpu, 64); |
289 |
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} else { |
290 |
dpavlin |
18 |
odata = d->irq_enable; |
291 |
dpavlin |
14 |
fatal("[ WARNING: footbridge read from " |
292 |
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"ENABLE SET? ]\n"); |
293 |
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exit(1); |
294 |
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} |
295 |
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break; |
296 |
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297 |
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case IRQ_ENABLE_CLEAR: |
298 |
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if (writeflag == MEM_WRITE) { |
299 |
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d->irq_enable &= ~idata; |
300 |
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cpu_interrupt(cpu, 64); |
301 |
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} else { |
302 |
dpavlin |
18 |
odata = d->irq_enable; |
303 |
dpavlin |
14 |
fatal("[ WARNING: footbridge read from " |
304 |
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"ENABLE CLEAR? ]\n"); |
305 |
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exit(1); |
306 |
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} |
307 |
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break; |
308 |
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|
309 |
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case FIQ_STATUS: |
310 |
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if (writeflag == MEM_READ) |
311 |
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odata = d->fiq_status & d->fiq_enable; |
312 |
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else { |
313 |
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fatal("[ WARNING: footbridge write to fiq status? ]\n"); |
314 |
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exit(1); |
315 |
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} |
316 |
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break; |
317 |
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318 |
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case FIQ_RAW_STATUS: |
319 |
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if (writeflag == MEM_READ) |
320 |
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odata = d->fiq_status; |
321 |
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else { |
322 |
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fatal("[ footbridge write to fiq_raw_status ]\n"); |
323 |
|
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exit(1); |
324 |
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} |
325 |
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break; |
326 |
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327 |
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case FIQ_ENABLE_SET: |
328 |
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if (writeflag == MEM_WRITE) |
329 |
|
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d->fiq_enable |= idata; |
330 |
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break; |
331 |
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|
332 |
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case FIQ_ENABLE_CLEAR: |
333 |
|
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if (writeflag == MEM_WRITE) |
334 |
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d->fiq_enable &= ~idata; |
335 |
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break; |
336 |
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|
337 |
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case TIMER_1_LOAD: |
338 |
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if (writeflag == MEM_READ) |
339 |
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odata = d->timer_load[timer_nr]; |
340 |
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else { |
341 |
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d->timer_value[timer_nr] = |
342 |
|
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d->timer_load[timer_nr] = idata & TIMER_MAX_VAL; |
343 |
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debug("[ footbridge: timer %i (1-based), value %i ]\n", |
344 |
|
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timer_nr + 1, (int)d->timer_value[timer_nr]); |
345 |
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d->timer_tick_countdown[timer_nr] = 1; |
346 |
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cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
347 |
|
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} |
348 |
|
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break; |
349 |
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|
350 |
|
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case TIMER_1_VALUE: |
351 |
|
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if (writeflag == MEM_READ) { |
352 |
dpavlin |
18 |
/* |
353 |
dpavlin |
20 |
* NOTE/TODO: This is INCORRECT but speeds up NetBSD |
354 |
|
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* and OpenBSD boot sequences: if the timer is polled |
355 |
|
|
* "very often" (such as during bootup), then this |
356 |
|
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* causes the timers to expire quickly. |
357 |
dpavlin |
18 |
*/ |
358 |
|
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d->timer_being_read = 1; |
359 |
|
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d->timer_poll_mode ++; |
360 |
dpavlin |
20 |
if (d->timer_poll_mode >= TIMER_POLL_THRESHOLD) { |
361 |
|
|
d->timer_poll_mode = TIMER_POLL_THRESHOLD; |
362 |
dpavlin |
18 |
dev_footbridge_tick(cpu, d); |
363 |
dpavlin |
20 |
dev_footbridge_tick(cpu, d); |
364 |
|
|
dev_footbridge_tick(cpu, d); |
365 |
|
|
} |
366 |
dpavlin |
14 |
odata = d->timer_value[timer_nr]; |
367 |
dpavlin |
18 |
d->timer_being_read = 0; |
368 |
dpavlin |
14 |
} else |
369 |
|
|
d->timer_value[timer_nr] = idata & TIMER_MAX_VAL; |
370 |
|
|
break; |
371 |
|
|
|
372 |
|
|
case TIMER_1_CONTROL: |
373 |
|
|
if (writeflag == MEM_READ) |
374 |
|
|
odata = d->timer_control[timer_nr]; |
375 |
|
|
else { |
376 |
|
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d->timer_control[timer_nr] = idata; |
377 |
|
|
if (idata & TIMER_FCLK_16 && |
378 |
|
|
idata & TIMER_FCLK_256) { |
379 |
|
|
fatal("TODO: footbridge timer: " |
380 |
|
|
"both 16 and 256?\n"); |
381 |
|
|
exit(1); |
382 |
|
|
} |
383 |
|
|
if (idata & TIMER_ENABLE) { |
384 |
|
|
d->timer_value[timer_nr] = |
385 |
|
|
d->timer_load[timer_nr]; |
386 |
|
|
d->timer_tick_countdown[timer_nr] = 1; |
387 |
|
|
} |
388 |
|
|
cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
389 |
|
|
} |
390 |
|
|
break; |
391 |
|
|
|
392 |
|
|
case TIMER_1_CLEAR: |
393 |
|
|
if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) { |
394 |
|
|
d->timer_value[timer_nr] = d->timer_load[timer_nr]; |
395 |
|
|
d->timer_tick_countdown[timer_nr] = 1; |
396 |
|
|
} |
397 |
|
|
cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
398 |
|
|
break; |
399 |
|
|
|
400 |
|
|
default:if (writeflag == MEM_READ) { |
401 |
|
|
fatal("[ footbridge: read from 0x%x ]\n", |
402 |
|
|
(int)relative_addr); |
403 |
|
|
} else { |
404 |
|
|
fatal("[ footbridge: write to 0x%x: 0x%llx ]\n", |
405 |
|
|
(int)relative_addr, (long long)idata); |
406 |
|
|
} |
407 |
|
|
} |
408 |
|
|
|
409 |
|
|
if (writeflag == MEM_READ) |
410 |
|
|
memory_writemax64(cpu, data, len, odata); |
411 |
|
|
|
412 |
|
|
return 1; |
413 |
|
|
} |
414 |
|
|
|
415 |
|
|
|
416 |
dpavlin |
22 |
DEVINIT(footbridge) |
417 |
dpavlin |
14 |
{ |
418 |
|
|
struct footbridge_data *d; |
419 |
|
|
uint64_t pci_addr = 0x7b000000; |
420 |
|
|
int i; |
421 |
|
|
|
422 |
|
|
d = malloc(sizeof(struct footbridge_data)); |
423 |
|
|
if (d == NULL) { |
424 |
|
|
fprintf(stderr, "out of memory\n"); |
425 |
|
|
exit(1); |
426 |
|
|
} |
427 |
|
|
memset(d, 0, sizeof(struct footbridge_data)); |
428 |
|
|
|
429 |
|
|
/* DC21285 register access: */ |
430 |
|
|
memory_device_register(devinit->machine->memory, devinit->name, |
431 |
|
|
devinit->addr, DEV_FOOTBRIDGE_LENGTH, |
432 |
dpavlin |
20 |
dev_footbridge_access, d, DM_DEFAULT, NULL); |
433 |
dpavlin |
14 |
|
434 |
dpavlin |
20 |
/* ISA interrupt status/acknowledgement: */ |
435 |
dpavlin |
14 |
memory_device_register(devinit->machine->memory, "footbridge_isa", |
436 |
dpavlin |
20 |
0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL); |
437 |
dpavlin |
14 |
|
438 |
|
|
/* The "fcom" console: */ |
439 |
dpavlin |
22 |
d->console_handle = console_start_slave(devinit->machine, "fcom", 0); |
440 |
dpavlin |
14 |
|
441 |
|
|
/* A PCI bus: */ |
442 |
dpavlin |
20 |
d->pcibus = bus_pci_init( |
443 |
dpavlin |
22 |
devinit->machine, |
444 |
dpavlin |
20 |
devinit->irq_nr, /* PCI controller irq */ |
445 |
|
|
0x7c000000, /* PCI device io offset */ |
446 |
|
|
0x80000000, /* PCI device mem offset */ |
447 |
|
|
0x00000000, /* PCI port base */ |
448 |
|
|
0x00000000, /* PCI mem base */ |
449 |
|
|
0, /* PCI irq base: TODO */ |
450 |
|
|
0x7c000000, /* ISA port base */ |
451 |
|
|
0x80000000, /* ISA mem base */ |
452 |
|
|
32); /* ISA port base */ |
453 |
dpavlin |
14 |
|
454 |
|
|
/* ... with some default devices for known machine types: */ |
455 |
|
|
switch (devinit->machine->machine_type) { |
456 |
|
|
case MACHINE_CATS: |
457 |
|
|
bus_pci_add(devinit->machine, d->pcibus, |
458 |
dpavlin |
20 |
devinit->machine->memory, 0xc0, 7, 0, "ali_m1543"); |
459 |
dpavlin |
14 |
bus_pci_add(devinit->machine, d->pcibus, |
460 |
dpavlin |
20 |
devinit->machine->memory, 0xc0, 10, 0, "dec21143"); |
461 |
|
|
bus_pci_add(devinit->machine, d->pcibus, |
462 |
|
|
devinit->machine->memory, 0xc0, 16, 0, "ali_m5229"); |
463 |
dpavlin |
14 |
break; |
464 |
|
|
case MACHINE_NETWINDER: |
465 |
|
|
bus_pci_add(devinit->machine, d->pcibus, |
466 |
dpavlin |
20 |
devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553"); |
467 |
dpavlin |
14 |
bus_pci_add(devinit->machine, d->pcibus, |
468 |
dpavlin |
20 |
devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105"); |
469 |
dpavlin |
30 |
memory_device_register(devinit->machine->memory, |
470 |
|
|
"footbridge_reset", 0x7c000338, 1, |
471 |
|
|
dev_footbridge_reset_access, d, DM_DEFAULT, NULL); |
472 |
dpavlin |
14 |
break; |
473 |
|
|
default:fatal("footbridge: unimplemented machine type.\n"); |
474 |
|
|
exit(1); |
475 |
|
|
} |
476 |
|
|
|
477 |
|
|
/* PCI configuration space: */ |
478 |
|
|
memory_device_register(devinit->machine->memory, |
479 |
|
|
"footbridge_pci", pci_addr, 0x1000000, |
480 |
dpavlin |
20 |
dev_footbridge_pci_access, d, DM_DEFAULT, NULL); |
481 |
dpavlin |
14 |
|
482 |
|
|
/* Timer ticks: */ |
483 |
|
|
for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
484 |
|
|
d->timer_control[i] = TIMER_MODE_PERIODIC; |
485 |
|
|
d->timer_load[i] = TIMER_MAX_VAL; |
486 |
|
|
} |
487 |
|
|
machine_add_tickfunction(devinit->machine, |
488 |
dpavlin |
24 |
dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT, 0.0); |
489 |
dpavlin |
14 |
|
490 |
|
|
devinit->return_ptr = d; |
491 |
|
|
return 1; |
492 |
|
|
} |
493 |
|
|
|