/[gxemul]/trunk/src/devices/dev_dreamcast_g2.c
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Contents of /trunk/src/devices/dev_dreamcast_g2.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 7766 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 /*
2 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_dreamcast_g2.c,v 1.4 2007/02/03 20:14:23 debug Exp $
29 *
30 * Dreamcast G2 bus.
31 *
32 * Register offsets are from KOS, NetBSD sources, etc.
33 *
34 * TODO:
35 * Figure out what all these registers do!
36 */
37
38 #include <stdio.h>
39 #include <stdlib.h>
40 #include <string.h>
41
42 #include "cpu.h"
43 #include "device.h"
44 #include "machine.h"
45 #include "memory.h"
46 #include "misc.h"
47
48
49 #ifdef UNSTABLE_DEVEL
50 #define debug fatal
51 #endif
52
53 #define NREGS (0x100/sizeof(uint32_t))
54
55 struct dreamcast_g2_data {
56 uint32_t dma_reg[NREGS];
57 uint32_t extdma_reg[NREGS];
58 uint32_t unknown_reg[NREGS];
59 };
60
61 /* dma_reg[] offsets: */
62 #define PVR_STATE 0x00
63 #define PVR_LEN 0x04
64 #define PVR_DST 0x08
65 #define PVR_LMMODE0 0x84
66 #define PVR_LMMODE1 0x88
67
68 /*
69 * External DMA: 4 channels
70 *
71 * Note: Addresses and sizes must be 32-byte aligned.
72 * DIR is 0 for CPU to External device, 1 for External to CPU.
73 * MODE should be 5 for transfers to/from the SPU.
74 */
75 #define EXTDMA_CTRL_EXT_ADDR 0x00 /* EXTDMA_CTRL_* are repeated */
76 #define EXTDMA_CTRL_SH4_ADDR 0x04 /* 4 times (once for each channel) */
77 #define EXTDMA_CTRL_SIZE 0x08
78 #define EXTDMA_CTRL_DIR 0x0c
79 #define EXTDMA_CTRL_MODE 0x10
80 #define EXTDMA_CTRL_CTRL1 0x14
81 #define EXTDMA_CTRL_CTRL2 0x18
82 #define EXTDMA_CTRL_UNKNOWN 0x1c
83
84 #define EXTDMA_WAITSTATE 0x90
85 #define EXTDMA_MAGIC 0xbc
86 #define EXTDMA_MAGIC_VALUE 0x4659404f
87
88 #define EXTDMA_STAT_EXT_ADDR 0xc0 /* EXTDMA_STAT_* are repeated 4 */
89 #define EXTDMA_STAT_SH4_ADDR 0xc4 /* times too */
90 #define EXTDMA_STAT_SIZE 0xc8
91 #define EXTDMA_STAT_STATUS 0xcc
92
93
94 DEVICE_ACCESS(dreamcast_g2)
95 {
96 struct dreamcast_g2_data *d = (struct dreamcast_g2_data *) extra;
97 uint64_t idata = 0, odata = 0;
98
99 if (writeflag == MEM_WRITE)
100 idata = memory_readmax64(cpu, data, len);
101
102 /* Default read: */
103 if (writeflag == MEM_READ)
104 odata = d->dma_reg[relative_addr / sizeof(uint32_t)];
105
106 switch (relative_addr) {
107
108 case PVR_LMMODE0: /* 0x84 */
109 case PVR_LMMODE1: /* 0x88 */
110 if (writeflag == MEM_WRITE) {
111 if (idata == 0) {
112 /* Done by IP.BIN during startup... */
113 } else {
114 fatal("[ dreamcast_g2: UNIMPLEMENTED write "
115 "0x84/0x88: TODO ]\n");
116 exit(1);
117 }
118 } else {
119 fatal("[ dreamcast_g2: read from 0x84/0x88: TODO ]\n");
120 exit(1);
121 }
122 break;
123
124 case 0x8c:
125 if (writeflag == MEM_WRITE) {
126 fatal("[ dreamcast_g2: write to 0x8c: TODO ]\n");
127 exit(1);
128 } else {
129 /* 0x20 means G2 DMA in progress? */
130 /* 0x11 = mask which has to do with AICA */
131 odata = 0x11 * (random() & 1);
132 }
133 break;
134
135 default:if (writeflag == MEM_READ) {
136 fatal("[ dreamcast_g2: read from addr 0x%x ]\n",
137 (int)relative_addr);
138 } else {
139 fatal("[ dreamcast_g2: write to addr 0x%x: 0x%x ]\n",
140 (int)relative_addr, (int)idata);
141 }
142 exit(1);
143 }
144
145 /* Default write: */
146 if (writeflag == MEM_WRITE)
147 d->dma_reg[relative_addr / sizeof(uint32_t)] = idata;
148
149 if (writeflag == MEM_READ)
150 memory_writemax64(cpu, data, len, odata);
151
152 return 1;
153 }
154
155
156 DEVICE_ACCESS(dreamcast_g2_extdma)
157 {
158 struct dreamcast_g2_data *d = (struct dreamcast_g2_data *) extra;
159 uint64_t idata = 0, odata = 0;
160 int reg = relative_addr, channel = 0;
161
162 if (writeflag == MEM_WRITE)
163 idata = memory_readmax64(cpu, data, len);
164
165 /* Default read: */
166 if (writeflag == MEM_READ)
167 odata = d->extdma_reg[relative_addr / sizeof(uint32_t)];
168
169 if (reg < 0x7f) {
170 channel = (reg >> 5) & 3;
171 reg &= 0x1f;
172 }
173
174 if (reg >= 0xc0 && reg < 0xff) {
175 channel = (reg >> 4) & 3;
176 reg = 0xc0 + (reg & 0xf);
177 }
178
179 switch (reg) {
180
181 case EXTDMA_WAITSTATE:
182 break;
183
184 case 0x94:
185 /* Written to by boot stage 1 in IP.BIN? */
186 if (writeflag == MEM_WRITE) {
187 if (idata != 0x271) {
188 fatal("Unimplemented write to extdma 0x94\n");
189 exit(1);
190 }
191 }
192 break;
193
194 default:if (writeflag == MEM_READ) {
195 fatal("[ dreamcast_g2_extdma: read from addr 0x%x ]\n",
196 (int)relative_addr);
197 } else {
198 fatal("[ dreamcast_g2_extdma: write to addr 0x%x: "
199 "0x%x ]\n", (int)relative_addr, (int)idata);
200 }
201 exit(1);
202 }
203
204 /* Default write: */
205 if (writeflag == MEM_WRITE)
206 d->extdma_reg[relative_addr / sizeof(uint32_t)] = idata;
207
208 if (writeflag == MEM_READ)
209 memory_writemax64(cpu, data, len, odata);
210
211 return 1;
212 }
213
214
215 DEVICE_ACCESS(dreamcast_g2_unknown)
216 {
217 struct dreamcast_g2_data *d = (struct dreamcast_g2_data *) extra;
218 uint64_t idata = 0, odata = 0;
219
220 if (writeflag == MEM_WRITE)
221 idata = memory_readmax64(cpu, data, len);
222
223 /* Default read: */
224 if (writeflag == MEM_READ)
225 odata = d->unknown_reg[relative_addr / sizeof(uint32_t)];
226
227 switch (relative_addr) {
228
229 case 0x90:
230 case 0x94:
231 if (writeflag != MEM_WRITE || idata != 0x222) {
232 fatal("[ dreamcast_g2_unknown: unimplemented 0x90 ]\n");
233 exit(1);
234 }
235 break;
236
237 case 0xa0:
238 case 0xa4:
239 if (writeflag != MEM_WRITE || idata != 0x2001) {
240 fatal("[ dreamcast_g2_unknown: unimplemented 0xa0 ]\n");
241 exit(1);
242 }
243 break;
244
245 case 0xe4:
246 /* Writing 0x1fffff resets a disabled GD-ROM drive? */
247 if (writeflag != MEM_WRITE || idata != 0x1fffff) {
248 fatal("[ dreamcast_g2_unknown: unimplemented 0xe4 ]\n");
249 exit(1);
250 }
251 break;
252
253 default:if (writeflag == MEM_READ) {
254 fatal("[ dreamcast_g2_unknown: read from addr 0x%x ]\n",
255 (int)relative_addr);
256 } else {
257 fatal("[ dreamcast_g2_unknown: write to addr 0x%x: "
258 "0x%x ]\n", (int)relative_addr, (int)idata);
259 }
260 exit(1);
261 }
262
263 /* Default write: */
264 if (writeflag == MEM_WRITE)
265 d->unknown_reg[relative_addr / sizeof(uint32_t)] = idata;
266
267 if (writeflag == MEM_READ)
268 memory_writemax64(cpu, data, len, odata);
269
270 return 1;
271 }
272
273
274 DEVINIT(dreamcast_g2)
275 {
276 struct machine *machine = devinit->machine;
277 struct dreamcast_g2_data *d = malloc(sizeof(struct dreamcast_g2_data));
278 if (d == NULL) {
279 fprintf(stderr, "out of memory\n");
280 exit(1);
281 }
282 memset(d, 0, sizeof(struct dreamcast_g2_data));
283
284 memory_device_register(machine->memory, devinit->name,
285 0x005f6800, 0x100, dev_dreamcast_g2_access, d, DM_DEFAULT, NULL);
286
287 memory_device_register(machine->memory, devinit->name, 0x005f7800,
288 0x100, dev_dreamcast_g2_extdma_access, d, DM_DEFAULT, NULL);
289
290 memory_device_register(machine->memory, devinit->name, 0x005f7400,
291 0x100, dev_dreamcast_g2_unknown_access, d, DM_DEFAULT, NULL);
292
293 return 1;
294 }
295
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