/[gxemul]/trunk/src/devices/dev_dec_ioasic.c
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Contents of /trunk/src/devices/dev_dec_ioasic.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 1 month ago) by dpavlin
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File size: 7752 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_dec_ioasic.c,v 1.15 2006/01/01 13:17:16 debug Exp $
29 *
30 * DECstation "3MIN" and "3MAX" IOASIC device.
31 *
32 * TODO: Lots of stuff, such as DMA and all bits in the control registers.
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38
39 #include "cpu.h"
40 #include "devices.h"
41 #include "memory.h"
42 #include "misc.h"
43
44 #include "dec_kn03.h"
45 #include "tc_ioasicreg.h"
46
47 #define IOASIC_DEBUG
48 /* #define debug fatal */
49
50 /*
51 * dev_dec_ioasic_access():
52 */
53 DEVICE_ACCESS(dec_ioasic)
54 {
55 struct dec_ioasic_data *d = (struct dec_ioasic_data *) extra;
56 uint64_t idata = 0, odata = 0;
57 uint64_t curptr;
58 int dma_len, dma_res;
59 uint32_t csr;
60 int regnr;
61
62 if (writeflag == MEM_WRITE)
63 idata = memory_readmax64(cpu, data, len);
64
65 regnr = (relative_addr - IOASIC_SLOT_1_START) / 0x10;
66 if (relative_addr < 0x80000 && (relative_addr & 0xf) != 0)
67 fatal("[ dec_ioasic: unaligned access? relative_addr = "
68 "0x%x ]\n", (int)relative_addr);
69
70 if (regnr >= 0 && regnr < N_DEC_IOASIC_REGS) {
71 if (writeflag == MEM_WRITE)
72 d->reg[regnr] = idata;
73 else
74 odata = d->reg[regnr];
75 }
76
77 #ifdef IOASIC_DEBUG
78 if (writeflag == MEM_WRITE)
79 debug("[ dec_ioasic: write to address 0x%llx, data=0x"
80 "%016llx ]\n", (long long)relative_addr, (long long)idata);
81 else
82 debug("[ dec_ioasic: read from address 0x%llx ]\n",
83 (long long)relative_addr);
84 #endif
85
86 switch (relative_addr) {
87
88 /* Don't print warnings for these: */
89 case IOASIC_SCSI_DMAPTR:
90 case IOASIC_SCC_T1_DMAPTR:
91 case IOASIC_SCC_T2_DMAPTR:
92 case IOASIC_SCC_R1_DMAPTR:
93 case IOASIC_SCC_R2_DMAPTR:
94 break;
95
96 case IOASIC_CSR:
97 if (writeflag == MEM_WRITE) {
98 csr = d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) / 0x10];
99
100 d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
101 ~IOASIC_INTR_T2_PAGE_END;
102
103 if (csr & IOASIC_CSR_DMAEN_T2) {
104 /* Transmit data: */
105 curptr = (d->reg[(IOASIC_SCC_T2_DMAPTR -
106 IOASIC_SLOT_1_START) / 0x10] >> 3)
107 | ((d->reg[(IOASIC_SCC_T2_DMAPTR -
108 IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
109 dma_len = 0x1000 - (curptr & 0xffc);
110
111 if ((curptr & 0xfff) == 0)
112 break;
113
114 if (d->dma_func[3] != NULL) {
115 d->dma_func[3](cpu,
116 d->dma_func_extra[3], curptr,
117 dma_len, 1);
118 } else
119 fatal("[ dec_ioasic: DMA tx: data @ "
120 "%08x, len %i bytes, but no "
121 "handler? ]\n", (int)curptr,
122 dma_len);
123
124 /* and signal the end of page: */
125 d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) /
126 0x10] |= IOASIC_INTR_T2_PAGE_END;
127
128 d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) /
129 0x10] &= ~IOASIC_CSR_DMAEN_T2;
130 curptr |= 0xfff;
131 curptr ++;
132
133 d->reg[(IOASIC_SCC_T2_DMAPTR -
134 IOASIC_SLOT_1_START) / 0x10] = ((curptr <<
135 3) & ~0x1f) | ((curptr >> 29) & 0x1f);
136 }
137
138 if (csr & IOASIC_CSR_DMAEN_R2) {
139 /* Receive data: */
140 curptr = (d->reg[(IOASIC_SCC_R2_DMAPTR -
141 IOASIC_SLOT_1_START) / 0x10] >> 3)
142 | ((d->reg[(IOASIC_SCC_R2_DMAPTR -
143 IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
144 dma_len = 0x1000 - (curptr & 0xffc);
145
146 dma_res = 0;
147 if (d->dma_func[3] != NULL) {
148 dma_res = d->dma_func[3](cpu,
149 d->dma_func_extra[3], curptr,
150 dma_len, 0);
151 } else
152 fatal("[ dec_ioasic: DMA tx: data @ "
153 "%08x, len %i bytes, but no "
154 "handler? ]\n", (int)curptr,
155 dma_len);
156
157 /* and signal the end of page: */
158 if (dma_res > 0) {
159 if ((curptr & 0x800) != ((curptr +
160 dma_res) & 0x800))
161 d->reg[(IOASIC_INTR -
162 IOASIC_SLOT_1_START) / 0x10]
163 |= IOASIC_INTR_R2_HALF_PAGE;
164 curptr += dma_res;
165 /* d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START
166 ) / 0x10] &= ~IOASIC_CSR_DMAEN_R2; */
167 d->reg[(IOASIC_SCC_R2_DMAPTR -
168 IOASIC_SLOT_1_START) / 0x10] =
169 ((curptr << 3) & ~0x1f) | ((curptr
170 >> 29) & 0x1f);
171 }
172 }
173 }
174 break;
175
176 case IOASIC_INTR:
177 if (writeflag == MEM_READ) {
178 odata = d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START)
179 / 0x10];
180 /* Note/TODO: How about other models than KN03? */
181 if (!d->rackmount_flag)
182 odata |= KN03_INTR_PROD_JUMPER;
183 } else {
184 /* Clear bits on write. */
185 d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
186 ~idata;
187
188 /* Make sure that the CPU interrupt is deasserted as
189 well: */
190 if (idata != 0)
191 cpu_interrupt_ack(cpu, 8 + idata);
192 }
193 break;
194
195 case IOASIC_IMSK:
196 if (writeflag == MEM_WRITE) {
197 d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / 0x10] =
198 idata;
199 cpu_interrupt_ack(cpu, 8 + 0);
200 } else
201 odata = d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) /
202 0x10];
203 break;
204
205 case IOASIC_CTR:
206 if (writeflag == MEM_READ)
207 odata = 0;
208 break;
209
210 case 0x80000:
211 case 0x80004:
212 case 0x80008:
213 case 0x8000c:
214 case 0x80010:
215 case 0x80014:
216 /* Station's ethernet address: */
217 if (writeflag == MEM_WRITE) {
218 fatal("[ dec_ioasic: attempt to write to the station's"
219 " ethernet address? ]\n");
220 } else {
221 odata = ((relative_addr - 0x80000) / 4 + 1) * 0x10;
222 }
223 break;
224
225 default:
226 if (writeflag == MEM_WRITE)
227 fatal("[ dec_ioasic: unimplemented write to address "
228 "0x%llx, data=0x%016llx ]\n",
229 (long long)relative_addr, (long long)idata);
230 else
231 fatal("[ dec_ioasic: unimplemented read from address "
232 "0x%llx ]\n", (long long)relative_addr);
233 }
234
235 if (writeflag == MEM_READ)
236 memory_writemax64(cpu, data, len, odata);
237
238 return 1;
239 }
240
241
242 /*
243 * dev_dec_ioasic_init():
244 *
245 * For DECstation "type 4", the rackmount_flag selects which model type
246 * the IOASIC should identify itself as (5000 for zero, 5900 if rackmount_flag
247 * is non-zero). It is probably not meaningful on other machines than
248 * type 4.
249 */
250 struct dec_ioasic_data *dev_dec_ioasic_init(struct cpu *cpu,
251 struct memory *mem, uint64_t baseaddr, int rackmount_flag)
252 {
253 struct dec_ioasic_data *d = malloc(sizeof(struct dec_ioasic_data));
254 if (d == NULL) {
255 fprintf(stderr, "out of memory\n");
256 exit(1);
257 }
258 memset(d, 0, sizeof(struct dec_ioasic_data));
259
260 d->rackmount_flag = rackmount_flag;
261
262 memory_device_register(mem, "dec_ioasic", baseaddr,
263 DEV_DEC_IOASIC_LENGTH, dev_dec_ioasic_access, (void *)d,
264 DM_DEFAULT, NULL);
265 return d;
266 }
267

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