/[gxemul]/trunk/src/devices/dev_dec_ioasic.c
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Annotation of /trunk/src/devices/dev_dec_ioasic.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 7764 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 dpavlin 4 /*
2 dpavlin 34 * Copyright (C) 2004-2007 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: dev_dec_ioasic.c,v 1.18 2007/06/15 18:44:19 debug Exp $
29 dpavlin 4 *
30 dpavlin 42 * COMMENT: IOASIC device used in the DECstation "3MIN" and "3MAX" machines
31     *
32 dpavlin 4 * TODO: Lots of stuff, such as DMA and all bits in the control registers.
33     */
34    
35     #include <stdio.h>
36     #include <stdlib.h>
37     #include <string.h>
38    
39     #include "cpu.h"
40     #include "devices.h"
41     #include "memory.h"
42     #include "misc.h"
43    
44     #include "dec_kn03.h"
45     #include "tc_ioasicreg.h"
46    
47     #define IOASIC_DEBUG
48     /* #define debug fatal */
49    
50 dpavlin 42
51 dpavlin 22 DEVICE_ACCESS(dec_ioasic)
52 dpavlin 4 {
53 dpavlin 42 struct dec_ioasic_data *d = extra;
54 dpavlin 4 uint64_t idata = 0, odata = 0;
55     uint64_t curptr;
56     uint32_t csr;
57 dpavlin 42 int dma_len, dma_res, regnr;
58 dpavlin 4
59 dpavlin 18 if (writeflag == MEM_WRITE)
60     idata = memory_readmax64(cpu, data, len);
61 dpavlin 4
62     regnr = (relative_addr - IOASIC_SLOT_1_START) / 0x10;
63     if (relative_addr < 0x80000 && (relative_addr & 0xf) != 0)
64     fatal("[ dec_ioasic: unaligned access? relative_addr = "
65     "0x%x ]\n", (int)relative_addr);
66    
67     if (regnr >= 0 && regnr < N_DEC_IOASIC_REGS) {
68     if (writeflag == MEM_WRITE)
69     d->reg[regnr] = idata;
70     else
71     odata = d->reg[regnr];
72     }
73    
74     #ifdef IOASIC_DEBUG
75     if (writeflag == MEM_WRITE)
76     debug("[ dec_ioasic: write to address 0x%llx, data=0x"
77     "%016llx ]\n", (long long)relative_addr, (long long)idata);
78     else
79     debug("[ dec_ioasic: read from address 0x%llx ]\n",
80     (long long)relative_addr);
81     #endif
82    
83     switch (relative_addr) {
84    
85     /* Don't print warnings for these: */
86     case IOASIC_SCSI_DMAPTR:
87     case IOASIC_SCC_T1_DMAPTR:
88     case IOASIC_SCC_T2_DMAPTR:
89     case IOASIC_SCC_R1_DMAPTR:
90     case IOASIC_SCC_R2_DMAPTR:
91     break;
92    
93     case IOASIC_CSR:
94     if (writeflag == MEM_WRITE) {
95     csr = d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) / 0x10];
96    
97     d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
98     ~IOASIC_INTR_T2_PAGE_END;
99    
100     if (csr & IOASIC_CSR_DMAEN_T2) {
101     /* Transmit data: */
102     curptr = (d->reg[(IOASIC_SCC_T2_DMAPTR -
103     IOASIC_SLOT_1_START) / 0x10] >> 3)
104     | ((d->reg[(IOASIC_SCC_T2_DMAPTR -
105     IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
106     dma_len = 0x1000 - (curptr & 0xffc);
107    
108     if ((curptr & 0xfff) == 0)
109     break;
110    
111     if (d->dma_func[3] != NULL) {
112     d->dma_func[3](cpu,
113     d->dma_func_extra[3], curptr,
114     dma_len, 1);
115     } else
116     fatal("[ dec_ioasic: DMA tx: data @ "
117     "%08x, len %i bytes, but no "
118     "handler? ]\n", (int)curptr,
119     dma_len);
120    
121     /* and signal the end of page: */
122     d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) /
123     0x10] |= IOASIC_INTR_T2_PAGE_END;
124    
125     d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) /
126     0x10] &= ~IOASIC_CSR_DMAEN_T2;
127     curptr |= 0xfff;
128     curptr ++;
129    
130     d->reg[(IOASIC_SCC_T2_DMAPTR -
131     IOASIC_SLOT_1_START) / 0x10] = ((curptr <<
132     3) & ~0x1f) | ((curptr >> 29) & 0x1f);
133     }
134    
135     if (csr & IOASIC_CSR_DMAEN_R2) {
136     /* Receive data: */
137     curptr = (d->reg[(IOASIC_SCC_R2_DMAPTR -
138     IOASIC_SLOT_1_START) / 0x10] >> 3)
139     | ((d->reg[(IOASIC_SCC_R2_DMAPTR -
140     IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
141     dma_len = 0x1000 - (curptr & 0xffc);
142    
143     dma_res = 0;
144     if (d->dma_func[3] != NULL) {
145     dma_res = d->dma_func[3](cpu,
146     d->dma_func_extra[3], curptr,
147     dma_len, 0);
148     } else
149     fatal("[ dec_ioasic: DMA tx: data @ "
150     "%08x, len %i bytes, but no "
151     "handler? ]\n", (int)curptr,
152     dma_len);
153    
154     /* and signal the end of page: */
155     if (dma_res > 0) {
156     if ((curptr & 0x800) != ((curptr +
157     dma_res) & 0x800))
158     d->reg[(IOASIC_INTR -
159     IOASIC_SLOT_1_START) / 0x10]
160     |= IOASIC_INTR_R2_HALF_PAGE;
161     curptr += dma_res;
162     /* d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START
163     ) / 0x10] &= ~IOASIC_CSR_DMAEN_R2; */
164     d->reg[(IOASIC_SCC_R2_DMAPTR -
165     IOASIC_SLOT_1_START) / 0x10] =
166     ((curptr << 3) & ~0x1f) | ((curptr
167     >> 29) & 0x1f);
168     }
169     }
170     }
171     break;
172    
173     case IOASIC_INTR:
174     if (writeflag == MEM_READ) {
175     odata = d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START)
176     / 0x10];
177     /* Note/TODO: How about other models than KN03? */
178     if (!d->rackmount_flag)
179     odata |= KN03_INTR_PROD_JUMPER;
180     } else {
181     /* Clear bits on write. */
182     d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
183     ~idata;
184    
185     /* Make sure that the CPU interrupt is deasserted as
186     well: */
187 dpavlin 34 fatal("TODO: interrupt rewrite!\n");
188     abort();
189     // if (idata != 0)
190     // cpu_interrupt_ack(cpu, 8 + idata);
191 dpavlin 4 }
192     break;
193    
194     case IOASIC_IMSK:
195     if (writeflag == MEM_WRITE) {
196     d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / 0x10] =
197     idata;
198 dpavlin 34 fatal("TODO: interrupt rewrite!\n");
199     abort();
200     // cpu_interrupt_ack(cpu, 8 + 0);
201 dpavlin 4 } else
202     odata = d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) /
203     0x10];
204     break;
205    
206     case IOASIC_CTR:
207     if (writeflag == MEM_READ)
208     odata = 0;
209     break;
210    
211     case 0x80000:
212     case 0x80004:
213     case 0x80008:
214     case 0x8000c:
215     case 0x80010:
216     case 0x80014:
217     /* Station's ethernet address: */
218     if (writeflag == MEM_WRITE) {
219     fatal("[ dec_ioasic: attempt to write to the station's"
220     " ethernet address? ]\n");
221     } else {
222     odata = ((relative_addr - 0x80000) / 4 + 1) * 0x10;
223     }
224     break;
225    
226     default:
227     if (writeflag == MEM_WRITE)
228     fatal("[ dec_ioasic: unimplemented write to address "
229     "0x%llx, data=0x%016llx ]\n",
230     (long long)relative_addr, (long long)idata);
231     else
232     fatal("[ dec_ioasic: unimplemented read from address "
233     "0x%llx ]\n", (long long)relative_addr);
234     }
235    
236     if (writeflag == MEM_READ)
237     memory_writemax64(cpu, data, len, odata);
238    
239     return 1;
240     }
241    
242    
243     /*
244     * dev_dec_ioasic_init():
245     *
246     * For DECstation "type 4", the rackmount_flag selects which model type
247     * the IOASIC should identify itself as (5000 for zero, 5900 if rackmount_flag
248     * is non-zero). It is probably not meaningful on other machines than
249     * type 4.
250     */
251     struct dec_ioasic_data *dev_dec_ioasic_init(struct cpu *cpu,
252     struct memory *mem, uint64_t baseaddr, int rackmount_flag)
253     {
254 dpavlin 42 struct dec_ioasic_data *d;
255    
256     CHECK_ALLOCATION(d = malloc(sizeof(struct dec_ioasic_data)));
257 dpavlin 4 memset(d, 0, sizeof(struct dec_ioasic_data));
258    
259     d->rackmount_flag = rackmount_flag;
260    
261     memory_device_register(mem, "dec_ioasic", baseaddr,
262     DEV_DEC_IOASIC_LENGTH, dev_dec_ioasic_access, (void *)d,
263 dpavlin 20 DM_DEFAULT, NULL);
264 dpavlin 42
265 dpavlin 4 return d;
266     }
267    

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