src/devices/dev_dec_ioasic.c

/*
 *  Copyright (C) 2004-2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_dec_ioasic.c,v 1.12 2005/02/22 20:18:30 debug Exp $
 *  
 *  DECstation "3MIN" and "3MAX" IOASIC device.
 *
 *  TODO:  Lots of stuff, such as DMA and all bits in the control registers.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "cpu.h"
#include "devices.h"
#include "memory.h"
#include "misc.h"

#include "dec_kn03.h"
#include "tc_ioasicreg.h"

#define IOASIC_DEBUG
/* #define debug fatal */

/*
 *  dev_dec_ioasic_access():
 */
int dev_dec_ioasic_access(struct cpu *cpu, struct memory *mem,
        uint64_t relative_addr, unsigned char *data, size_t len,
        int writeflag, void *extra)
{
        struct dec_ioasic_data *d = (struct dec_ioasic_data *) extra;
        uint64_t idata = 0, odata = 0;
        uint64_t curptr;
        int dma_len, dma_res;
        uint32_t csr;
        int regnr;

        idata = memory_readmax64(cpu, data, len);

        regnr = (relative_addr - IOASIC_SLOT_1_START) / 0x10;
        if (relative_addr < 0x80000 && (relative_addr & 0xf) != 0)
                fatal("[ dec_ioasic: unaligned access? relative_addr = "
                    "0x%x ]\n", (int)relative_addr);

        if (regnr >= 0 && regnr < N_DEC_IOASIC_REGS) {
                if (writeflag == MEM_WRITE)
                        d->reg[regnr] = idata;
                else
                        odata = d->reg[regnr];
        }

#ifdef IOASIC_DEBUG
        if (writeflag == MEM_WRITE)
                debug("[ dec_ioasic: write to address 0x%llx, data=0x"
                    "%016llx ]\n", (long long)relative_addr, (long long)idata);
        else
                debug("[ dec_ioasic: read from address 0x%llx ]\n",
                    (long long)relative_addr);
#endif

        switch (relative_addr) {

        /*  Don't print warnings for these:  */
        case IOASIC_SCSI_DMAPTR:
        case IOASIC_SCC_T1_DMAPTR:
        case IOASIC_SCC_T2_DMAPTR:
        case IOASIC_SCC_R1_DMAPTR:
        case IOASIC_SCC_R2_DMAPTR:
                break;

        case IOASIC_CSR:
                if (writeflag == MEM_WRITE) {
                        csr = d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) / 0x10];

                        d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
                            ~IOASIC_INTR_T2_PAGE_END;

                        if (csr & IOASIC_CSR_DMAEN_T2) {
                                /*  Transmit data:  */
                                curptr = (d->reg[(IOASIC_SCC_T2_DMAPTR -
                                    IOASIC_SLOT_1_START) / 0x10] >> 3)
                                    | ((d->reg[(IOASIC_SCC_T2_DMAPTR -
                                    IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
                                dma_len = 0x1000 - (curptr & 0xffc);

                                if ((curptr & 0xfff) == 0)
                                        break;

                                if (d->dma_func[3] != NULL) {
                                        d->dma_func[3](cpu,
                                            d->dma_func_extra[3], curptr,
                                            dma_len, 1);
                                } else
                                        fatal("[ dec_ioasic: DMA tx: data @ "
                                            "%08x, len %i bytes, but no "
                                            "handler? ]\n", (int)curptr,
                                            dma_len);

                                /*  and signal the end of page:  */
                                d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) /
                                    0x10] |= IOASIC_INTR_T2_PAGE_END;

                                d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) /
                                    0x10] &= ~IOASIC_CSR_DMAEN_T2;
                                curptr |= 0xfff;
                                curptr ++;

                                d->reg[(IOASIC_SCC_T2_DMAPTR -
                                    IOASIC_SLOT_1_START) / 0x10] = ((curptr <<
                                    3) & ~0x1f) | ((curptr >> 29) & 0x1f);
                        }

                        if (csr & IOASIC_CSR_DMAEN_R2) {
                                /*  Receive data:  */
                                curptr = (d->reg[(IOASIC_SCC_R2_DMAPTR -
                                    IOASIC_SLOT_1_START) / 0x10] >> 3)
                                    | ((d->reg[(IOASIC_SCC_R2_DMAPTR -
                                    IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
                                dma_len = 0x1000 - (curptr & 0xffc);

                                dma_res = 0;
                                if (d->dma_func[3] != NULL) {
                                        dma_res = d->dma_func[3](cpu,
                                            d->dma_func_extra[3], curptr,
                                            dma_len, 0);
                                } else
                                        fatal("[ dec_ioasic: DMA tx: data @ "
                                            "%08x, len %i bytes, but no "
                                            "handler? ]\n", (int)curptr,
                                            dma_len);

                                /*  and signal the end of page:  */
                                if (dma_res > 0) {
                                        if ((curptr & 0x800) != ((curptr +
                                            dma_res) & 0x800))
                                                d->reg[(IOASIC_INTR -
                                                    IOASIC_SLOT_1_START) / 0x10]
                                                    |= IOASIC_INTR_R2_HALF_PAGE;
                                        curptr += dma_res;
/*                                      d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START
                                           ) / 0x10] &= ~IOASIC_CSR_DMAEN_R2; */
                                        d->reg[(IOASIC_SCC_R2_DMAPTR -
                                            IOASIC_SLOT_1_START) / 0x10] =
                                            ((curptr << 3) & ~0x1f) | ((curptr
                                            >> 29) & 0x1f);
                                }
                        }
                }
                break;

        case IOASIC_INTR:
                if (writeflag == MEM_READ) {
                        odata = d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START)
                            / 0x10];
                        /*  Note/TODO: How about other models than KN03?  */
                        if (!d->rackmount_flag)
                                odata |= KN03_INTR_PROD_JUMPER;
                } else {
                        /*  Clear bits on write.  */
                        d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
                            ~idata;

                        /*  Make sure that the CPU interrupt is deasserted as
                            well:  */
                        if (idata != 0)
                                cpu_interrupt_ack(cpu, 8 + idata);
                }
                break;

        case IOASIC_IMSK:
                if (writeflag == MEM_WRITE) {
                        d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / 0x10] =
                            idata;
                        cpu_interrupt_ack(cpu, 8 + 0);
                } else
                        odata = d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) /
                            0x10];
                break;

        case IOASIC_CTR:
                if (writeflag == MEM_READ)
                        odata = 0;
                break;

        case 0x80000:
        case 0x80004:
        case 0x80008:
        case 0x8000c:
        case 0x80010:
        case 0x80014:
                /*  Station's ethernet address:  */
                if (writeflag == MEM_WRITE) {
                        fatal("[ dec_ioasic: attempt to write to the station's"
                            " ethernet address? ]\n");
                } else {
                        odata = ((relative_addr - 0x80000) / 4 + 1) * 0x10;
                }
                break;

        default:
                if (writeflag == MEM_WRITE)
                        fatal("[ dec_ioasic: unimplemented write to address "
                            "0x%llx, data=0x%016llx ]\n",
                            (long long)relative_addr, (long long)idata);
                else
                        fatal("[ dec_ioasic: unimplemented read from address "
                            "0x%llx ]\n", (long long)relative_addr);
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


/*
 *  dev_dec_ioasic_init():
 *
 *  For DECstation "type 4", the rackmount_flag selects which model type
 *  the IOASIC should identify itself as (5000 for zero, 5900 if rackmount_flag
 *  is non-zero). It is probably not meaningful on other machines than
 *  type 4.
 */
struct dec_ioasic_data *dev_dec_ioasic_init(struct cpu *cpu,
        struct memory *mem, uint64_t baseaddr, int rackmount_flag)
{
        struct dec_ioasic_data *d = malloc(sizeof(struct dec_ioasic_data));
        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct dec_ioasic_data));

        d->rackmount_flag = rackmount_flag;

        memory_device_register(mem, "dec_ioasic", baseaddr,
            DEV_DEC_IOASIC_LENGTH, dev_dec_ioasic_access, (void *)d,
            MEM_DEFAULT, NULL);
        return d;
}

1	/*
2	* Copyright (C) 2004-2005 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: dev_dec_ioasic.c,v 1.12 2005/02/22 20:18:30 debug Exp $
29	*
30	* DECstation "3MIN" and "3MAX" IOASIC device.
31	*
32	* TODO: Lots of stuff, such as DMA and all bits in the control registers.
33	*/
34
35	#include <stdio.h>
36	#include <stdlib.h>
37	#include <string.h>
38
39	#include "cpu.h"
40	#include "devices.h"
41	#include "memory.h"
42	#include "misc.h"
43
44	#include "dec_kn03.h"
45	#include "tc_ioasicreg.h"
46
47	#define IOASIC_DEBUG
48	/* #define debug fatal */
49
50	/*
51	* dev_dec_ioasic_access():
52	*/
53	int dev_dec_ioasic_access(struct cpu cpu, struct memory mem,
54	uint64_t relative_addr, unsigned char *data, size_t len,
55	int writeflag, void *extra)
56	{
57	struct dec_ioasic_data d = (struct dec_ioasic_data ) extra;
58	uint64_t idata = 0, odata = 0;
59	uint64_t curptr;
60	int dma_len, dma_res;
61	uint32_t csr;
62	int regnr;
63
64	idata = memory_readmax64(cpu, data, len);
65
66	regnr = (relative_addr - IOASIC_SLOT_1_START) / 0x10;
67	if (relative_addr < 0x80000 && (relative_addr & 0xf) != 0)
68	fatal("[ dec_ioasic: unaligned access? relative_addr = "
69	"0x%x ]\n", (int)relative_addr);
70
71	if (regnr >= 0 && regnr < N_DEC_IOASIC_REGS) {
72	if (writeflag == MEM_WRITE)
73	d->reg[regnr] = idata;
74	else
75	odata = d->reg[regnr];
76	}
77
78	#ifdef IOASIC_DEBUG
79	if (writeflag == MEM_WRITE)
80	debug("[ dec_ioasic: write to address 0x%llx, data=0x"
81	"%016llx ]\n", (long long)relative_addr, (long long)idata);
82	else
83	debug("[ dec_ioasic: read from address 0x%llx ]\n",
84	(long long)relative_addr);
85	#endif
86
87	switch (relative_addr) {
88
89	/* Don't print warnings for these: */
90	case IOASIC_SCSI_DMAPTR:
91	case IOASIC_SCC_T1_DMAPTR:
92	case IOASIC_SCC_T2_DMAPTR:
93	case IOASIC_SCC_R1_DMAPTR:
94	case IOASIC_SCC_R2_DMAPTR:
95	break;
96
97	case IOASIC_CSR:
98	if (writeflag == MEM_WRITE) {
99	csr = d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) / 0x10];
100
101	d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
102	~IOASIC_INTR_T2_PAGE_END;
103
104	if (csr & IOASIC_CSR_DMAEN_T2) {
105	/* Transmit data: */
106	curptr = (d->reg[(IOASIC_SCC_T2_DMAPTR -
107	IOASIC_SLOT_1_START) / 0x10] >> 3)
108	\| ((d->reg[(IOASIC_SCC_T2_DMAPTR -
109	IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
110	dma_len = 0x1000 - (curptr & 0xffc);
111
112	if ((curptr & 0xfff) == 0)
113	break;
114
115	if (d->dma_func[3] != NULL) {
116	d->dma_func[3](cpu,
117	d->dma_func_extra[3], curptr,
118	dma_len, 1);
119	} else
120	fatal("[ dec_ioasic: DMA tx: data @ "
121	"%08x, len %i bytes, but no "
122	"handler? ]\n", (int)curptr,
123	dma_len);
124
125	/* and signal the end of page: */
126	d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) /
127	0x10] \|= IOASIC_INTR_T2_PAGE_END;
128
129	d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) /
130	0x10] &= ~IOASIC_CSR_DMAEN_T2;
131	curptr \|= 0xfff;
132	curptr ++;
133
134	d->reg[(IOASIC_SCC_T2_DMAPTR -
135	IOASIC_SLOT_1_START) / 0x10] = ((curptr <<
136	3) & ~0x1f) \| ((curptr >> 29) & 0x1f);
137	}
138
139	if (csr & IOASIC_CSR_DMAEN_R2) {
140	/* Receive data: */
141	curptr = (d->reg[(IOASIC_SCC_R2_DMAPTR -
142	IOASIC_SLOT_1_START) / 0x10] >> 3)
143	\| ((d->reg[(IOASIC_SCC_R2_DMAPTR -
144	IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
145	dma_len = 0x1000 - (curptr & 0xffc);
146
147	dma_res = 0;
148	if (d->dma_func[3] != NULL) {
149	dma_res = d->dma_func[3](cpu,
150	d->dma_func_extra[3], curptr,
151	dma_len, 0);
152	} else
153	fatal("[ dec_ioasic: DMA tx: data @ "
154	"%08x, len %i bytes, but no "
155	"handler? ]\n", (int)curptr,
156	dma_len);
157
158	/* and signal the end of page: */
159	if (dma_res > 0) {
160	if ((curptr & 0x800) != ((curptr +
161	dma_res) & 0x800))
162	d->reg[(IOASIC_INTR -
163	IOASIC_SLOT_1_START) / 0x10]
164	\|= IOASIC_INTR_R2_HALF_PAGE;
165	curptr += dma_res;
166	/* d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START
167	) / 0x10] &= ~IOASIC_CSR_DMAEN_R2; */
168	d->reg[(IOASIC_SCC_R2_DMAPTR -
169	IOASIC_SLOT_1_START) / 0x10] =
170	((curptr << 3) & ~0x1f) \| ((curptr
171	>> 29) & 0x1f);
172	}
173	}
174	}
175	break;
176
177	case IOASIC_INTR:
178	if (writeflag == MEM_READ) {
179	odata = d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START)
180	/ 0x10];
181	/* Note/TODO: How about other models than KN03? */
182	if (!d->rackmount_flag)
183	odata \|= KN03_INTR_PROD_JUMPER;
184	} else {
185	/* Clear bits on write. */
186	d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
187	~idata;
188
189	/* Make sure that the CPU interrupt is deasserted as
190	well: */
191	if (idata != 0)
192	cpu_interrupt_ack(cpu, 8 + idata);
193	}
194	break;
195
196	case IOASIC_IMSK:
197	if (writeflag == MEM_WRITE) {
198	d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / 0x10] =
199	idata;
200	cpu_interrupt_ack(cpu, 8 + 0);
201	} else
202	odata = d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) /
203	0x10];
204	break;
205
206	case IOASIC_CTR:
207	if (writeflag == MEM_READ)
208	odata = 0;
209	break;
210
211	case 0x80000:
212	case 0x80004:
213	case 0x80008:
214	case 0x8000c:
215	case 0x80010:
216	case 0x80014:
217	/* Station's ethernet address: */
218	if (writeflag == MEM_WRITE) {
219	fatal("[ dec_ioasic: attempt to write to the station's"
220	" ethernet address? ]\n");
221	} else {
222	odata = ((relative_addr - 0x80000) / 4 + 1) * 0x10;
223	}
224	break;
225
226	default:
227	if (writeflag == MEM_WRITE)
228	fatal("[ dec_ioasic: unimplemented write to address "
229	"0x%llx, data=0x%016llx ]\n",
230	(long long)relative_addr, (long long)idata);
231	else
232	fatal("[ dec_ioasic: unimplemented read from address "
233	"0x%llx ]\n", (long long)relative_addr);
234	}
235
236	if (writeflag == MEM_READ)
237	memory_writemax64(cpu, data, len, odata);
238
239	return 1;
240	}
241
242
243	/*
244	* dev_dec_ioasic_init():
245	*
246	* For DECstation "type 4", the rackmount_flag selects which model type
247	* the IOASIC should identify itself as (5000 for zero, 5900 if rackmount_flag
248	* is non-zero). It is probably not meaningful on other machines than
249	* type 4.
250	*/
251	struct dec_ioasic_data dev_dec_ioasic_init(struct cpu cpu,
252	struct memory *mem, uint64_t baseaddr, int rackmount_flag)
253	{
254	struct dec_ioasic_data *d = malloc(sizeof(struct dec_ioasic_data));
255	if (d == NULL) {
256	fprintf(stderr, "out of memory\n");
257	exit(1);
258	}
259	memset(d, 0, sizeof(struct dec_ioasic_data));
260
261	d->rackmount_flag = rackmount_flag;
262
263	memory_device_register(mem, "dec_ioasic", baseaddr,
264	DEV_DEC_IOASIC_LENGTH, dev_dec_ioasic_access, (void *)d,
265	MEM_DEFAULT, NULL);
266	return d;
267	}
268