/[gxemul]/trunk/src/devices/dev_dec5800.c
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Contents of /trunk/src/devices/dev_dec5800.c

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (12 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 12353 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============


1 /*
2 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_dec5800.c,v 1.15 2005/02/22 06:26:10 debug Exp $
29 *
30 * Emulation of devices found in a DECsystem 58x0, where x is the number
31 * of CPUs in the system. (The CPU board is called KN5800 by Ultrix.)
32 *
33 * o) timers and misc stuff
34 * o) BI (Backplane Interconnect)
35 * o) CCA (Console Communication Area)
36 * o) XMI (Extended Memory Interconnect)
37 *
38 * TODO: This hardware is not very easy to find docs about.
39 * Perhaps VAX 6000/300 docs?
40 */
41
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <string.h>
45
46 #include "console.h"
47 #include "cpu.h"
48 #include "devices.h"
49 #include "machine.h"
50 #include "memory.h"
51 #include "misc.h"
52
53
54 /*
55 * dev_dec5800_tick():
56 */
57 void dev_dec5800_tick(struct cpu *cpu, void *extra)
58 {
59 struct dec5800_data *d = extra;
60
61 /* Timer interrupts? */
62 if (d->csr & 0x8000) {
63 debug("[ dec5800: timer interrupt! ]\n");
64
65 /* Set timer interrupt pending bit: */
66 d->csr |= 0x20000000;
67
68 cpu_interrupt(cpu, 3);
69 }
70 }
71
72
73 /*
74 * dev_dec5800_vectors_access():
75 */
76 int dev_dec5800_vectors_access(struct cpu *cpu, struct memory *mem,
77 uint64_t relative_addr, unsigned char *data, size_t len,
78 int writeflag, void *extra)
79 {
80 uint64_t idata = 0, odata = 0;
81 struct dec5800_data *d = extra;
82
83 idata = memory_readmax64(cpu, data, len);
84
85 if (writeflag == MEM_READ) {
86 /* TODO */
87 /* 0xfc = transmit interrupt, 0xf8 = receive interrupt,
88 0x80 = IPI */
89 odata = d->vector_0x50;
90 /* odata = 0xfc; */
91 debug("[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n",
92 (int)relative_addr, (int)odata);
93 } else {
94 d->vector_0x50 = idata;
95 debug("[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n",
96 (int)relative_addr, (int)idata);
97 }
98
99 if (writeflag == MEM_READ)
100 memory_writemax64(cpu, data, len, odata);
101
102 return 1;
103 }
104
105
106 /*
107 * dev_dec5800_access():
108 */
109 int dev_dec5800_access(struct cpu *cpu, struct memory *mem,
110 uint64_t relative_addr, unsigned char *data, size_t len,
111 int writeflag, void *extra)
112 {
113 uint64_t idata = 0, odata = 0;
114 struct dec5800_data *d = extra;
115
116 idata = memory_readmax64(cpu, data, len);
117
118 /* Lowest 4 bits of csr contain cpu id: */
119 d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf);
120
121 switch (relative_addr) {
122 case 0x0000: /* csr */
123 if (writeflag == MEM_READ) {
124 odata = d->csr;
125 odata ^= random() & 0x10000;
126 debug("[ dec5800: read from csr: 0x%08x ]\n",
127 (int)odata);
128 } else {
129 d->csr = idata;
130
131 /* Ack. timer interrupts: */
132 d->csr &= ~0x20000000;
133 cpu_interrupt_ack(cpu, 3);
134
135 debug("[ dec5800: write to csr: 0x%08x ]\n",
136 (int)idata);
137 }
138 break;
139 default:
140 if (writeflag==MEM_READ) {
141 debug("[ dec5800: read from 0x%08lx ]\n",
142 (long)relative_addr);
143 } else {
144 debug("[ dec5800: write to 0x%08lx: 0x%08x ]\n",
145 (long)relative_addr, (int)idata);
146 }
147 }
148
149 if (writeflag == MEM_READ)
150 memory_writemax64(cpu, data, len, odata);
151
152 return 1;
153 }
154
155
156 /*
157 * dev_dec5800_init():
158 */
159 struct dec5800_data *dev_dec5800_init(struct machine *machine,
160 struct memory *mem, uint64_t baseaddr)
161 {
162 struct dec5800_data *d;
163
164 d = malloc(sizeof(struct dec5800_data));
165 if (d == NULL) {
166 fprintf(stderr, "out of memory\n");
167 exit(1);
168 }
169 memset(d, 0, sizeof(struct dec5800_data));
170
171 memory_device_register(mem, "dec5800", baseaddr,
172 DEV_DEC5800_LENGTH, dev_dec5800_access, d, MEM_DEFAULT, NULL);
173 memory_device_register(mem, "dec5800_vectors",
174 baseaddr + 0x30000000, 0x100, dev_dec5800_vectors_access,
175 d, MEM_DEFAULT, NULL);
176 machine_add_tickfunction(machine, dev_dec5800_tick, d, 14);
177
178 return d;
179 }
180
181
182 /*****************************************************************************/
183
184
185 #include "bireg.h"
186
187 struct decbi_data {
188 int csr[NNODEBI];
189 };
190
191
192 /*
193 * dev_decbi_access():
194 */
195 int dev_decbi_access(struct cpu *cpu, struct memory *mem,
196 uint64_t relative_addr, unsigned char *data, size_t len,
197 int writeflag, void *extra)
198 {
199 uint64_t idata = 0, odata = 0;
200 int node_nr;
201 struct decbi_data *d = extra;
202
203 idata = memory_readmax64(cpu, data, len);
204
205 relative_addr += BI_NODESIZE; /* HACK */
206
207 node_nr = relative_addr / BI_NODESIZE;
208 relative_addr &= (BI_NODESIZE - 1);
209
210 /* TODO: This "1" here is the max node number in actual use. */
211 if (node_nr > 1 || node_nr >= NNODEBI)
212 return 0;
213
214 switch (relative_addr) {
215 case BIREG_DTYPE:
216 if (writeflag==MEM_READ) {
217 /*
218 * This is a list of the devices in our BI slots:
219 */
220 switch (node_nr) {
221 case 1: odata = BIDT_KDB50; break; /* Disk */
222 /* case 2: odata = BIDT_DEBNA; break; */
223 /* BIDT_DEBNA = Ethernet */
224 /* case 3: odata = BIDT_MS820; break; */
225 /* BIDT_MS820 = Memory */
226 default:
227 /* No device. */
228 odata = 0;
229 }
230
231 debug("[ decbi: (node %i) read from BIREG_DTYPE:"
232 " 0x%x ]\n", node_nr, (int)odata);
233 } else {
234 debug("[ decbi: (node %i) attempt to write to "
235 "BIREG_DTYPE: 0x%08x ]\n", node_nr, (int)idata);
236 }
237 break;
238 case BIREG_VAXBICSR:
239 if (writeflag==MEM_READ) {
240 odata = (d->csr[node_nr] & ~BICSR_NODEMASK) | node_nr;
241 debug("[ decbi: (node %i) read from BIREG_"
242 "VAXBICSR: 0x%x ]\n", node_nr, (int)odata);
243 } else {
244 d->csr[node_nr] = idata;
245 debug("[ decbi: (node %i) attempt to write to "
246 "BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (int)idata);
247 }
248 break;
249 case 0xf4:
250 if (writeflag==MEM_READ) {
251 odata = 0xffff; /* ? */
252 debug("[ decbi: (node %i) read from 0xf4: "
253 "0x%x ]\n", node_nr, (int)odata);
254 } else {
255 debug("[ decbi: (node %i) attempt to write "
256 "to 0xf4: 0x%08x ]\n", node_nr, (int)idata);
257 }
258 break;
259 default:
260 if (writeflag==MEM_READ) {
261 debug("[ decbi: (node %i) read from unimplemented "
262 "0x%08lx ]\n", node_nr, (long)relative_addr,
263 (int)odata);
264 } else {
265 debug("[ decbi: (node %i) write to unimplemented "
266 "0x%08lx: 0x%08x ]\n", node_nr,
267 (long)relative_addr, (int)idata);
268 }
269 }
270
271 if (writeflag == MEM_READ)
272 memory_writemax64(cpu, data, len, odata);
273
274 return 1;
275 }
276
277
278 /*
279 * dev_decbi_init():
280 */
281 void dev_decbi_init(struct memory *mem, uint64_t baseaddr)
282 {
283 struct decbi_data *d;
284
285 d = malloc(sizeof(struct decbi_data));
286 if (d == NULL) {
287 fprintf(stderr, "out of memory\n");
288 exit(1);
289 }
290 memset(d, 0, sizeof(struct decbi_data));
291
292 memory_device_register(mem, "decbi", baseaddr + 0x2000,
293 DEV_DECBI_LENGTH - 0x2000, dev_decbi_access, d, MEM_DEFAULT, NULL);
294 }
295
296
297 /*****************************************************************************/
298
299
300 /*
301 * CCA, "Console Communication Area" for a DEC 5800 SMP system.
302 */
303
304 struct deccca_data {
305 int dummy;
306 };
307
308
309 /*
310 * dev_deccca_access():
311 */
312 int dev_deccca_access(struct cpu *cpu, struct memory *mem,
313 uint64_t relative_addr, unsigned char *data, size_t len,
314 int writeflag, void *extra)
315 {
316 uint64_t idata = 0, odata = 0;
317 /* struct deccca_data *d = extra; */
318
319 idata = memory_readmax64(cpu, data, len);
320
321 switch (relative_addr) {
322 case 6:
323 case 7:
324 /* CCA "ID" bytes? These must be here, or Ultrix complains. */
325 if (writeflag == MEM_READ)
326 odata = 67;
327 break;
328 case 8:
329 if (writeflag == MEM_READ)
330 odata = cpu->machine->ncpus;
331 break;
332 case 20:
333 if (writeflag == MEM_READ)
334 odata = (1 << cpu->machine->ncpus) - 1;
335 /* one bit for each cpu */
336 break;
337 case 28:
338 if (writeflag == MEM_READ)
339 odata = (1 << cpu->machine->ncpus) - 1;
340 /* one bit for each enabled(?) cpu */
341 break;
342 default:
343 if (writeflag==MEM_READ) {
344 debug("[ deccca: read from 0x%08lx ]\n",
345 (long)relative_addr);
346 } else {
347 debug("[ deccca: write to 0x%08lx: 0x%08x ]\n",
348 (long)relative_addr, (int)idata);
349 }
350 }
351
352 if (writeflag == MEM_READ)
353 memory_writemax64(cpu, data, len, odata);
354
355 return 1;
356 }
357
358
359 /*
360 * dev_deccca_init():
361 */
362 void dev_deccca_init(struct memory *mem, uint64_t baseaddr)
363 {
364 struct deccca_data *d;
365
366 d = malloc(sizeof(struct deccca_data));
367 if (d == NULL) {
368 fprintf(stderr, "out of memory\n");
369 exit(1);
370 }
371 memset(d, 0, sizeof(struct deccca_data));
372
373 memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH,
374 dev_deccca_access, d, MEM_DEFAULT, NULL);
375 }
376
377
378 /*****************************************************************************/
379
380
381 /*
382 * DEC 5800 XMI (this has to do with SMP...)
383 */
384
385 #include "xmireg.h"
386
387 struct decxmi_data {
388 uint32_t reg_0xc[NNODEXMI];
389 };
390
391
392 /*
393 * dev_decxmi_access():
394 */
395 int dev_decxmi_access(struct cpu *cpu, struct memory *mem,
396 uint64_t relative_addr, unsigned char *data, size_t len,
397 int writeflag, void *extra)
398 {
399 uint64_t idata = 0, odata = 0;
400 int node_nr;
401 struct decxmi_data *d = extra;
402
403 idata = memory_readmax64(cpu, data, len);
404
405 node_nr = relative_addr / XMI_NODESIZE;
406 relative_addr &= (XMI_NODESIZE - 1);
407
408 if (node_nr >= cpu->machine->ncpus + 1 || node_nr >= NNODEXMI)
409 return 0;
410
411 switch (relative_addr) {
412 case XMI_TYPE:
413 if (writeflag == MEM_READ) {
414 /*
415 * The first node is an XMI->BI adapter node, and then
416 * there are n CPU nodes.
417 */
418 odata = XMIDT_ISIS;
419 if (node_nr == 0)
420 odata = XMIDT_DWMBA;
421
422 debug("[ decxmi: (node %i) read from XMI_TYPE: "
423 "0x%08x ]\n", node_nr, (int)odata);
424 } else
425 debug("[ decxmi: (node %i) write to XMI_TYPE: "
426 "0x%08x ]\n", node_nr, (int)idata);
427 break;
428 case XMI_BUSERR:
429 if (writeflag == MEM_READ) {
430 odata = 0;
431 debug("[ decxmi: (node %i) read from XMI_BUSERR: "
432 "0x%08x ]\n", node_nr, (int)odata);
433 } else
434 debug("[ decxmi: (node %i) write to XMI_BUSERR: "
435 "0x%08x ]\n", node_nr, (int)idata);
436 break;
437 case XMI_FAIL:
438 if (writeflag == MEM_READ) {
439 odata = 0;
440 debug("[ decxmi: (node %i) read from XMI_FAIL: "
441 "0x%08x ]\n", node_nr, (int)odata);
442 } else
443 debug("[ decxmi: (node %i) write to XMI_FAIL: "
444 "0x%08x ]\n", node_nr, (int)idata);
445 break;
446 case 0xc:
447 if (writeflag == MEM_READ) {
448 odata = d->reg_0xc[node_nr];
449 debug("[ decxmi: (node %i) read from REG 0xC: "
450 "0x%08x ]\n", node_nr, (int)odata);
451 } else {
452 d->reg_0xc[node_nr] = idata;
453 debug("[ decxmi: (node %i) write to REG 0xC: "
454 "0x%08x ]\n", node_nr, (int)idata);
455 }
456 break;
457 default:
458 if (writeflag==MEM_READ) {
459 debug("[ decxmi: (node %i) read from unimplemented "
460 "0x%08lx ]\n", node_nr, (long)relative_addr,
461 (int)odata);
462 } else {
463 debug("[ decxmi: (node %i) write to unimplemented "
464 "0x%08lx: 0x%08x ]\n", node_nr,
465 (long)relative_addr, (int)idata);
466 }
467 }
468
469 if (writeflag == MEM_READ)
470 memory_writemax64(cpu, data, len, odata);
471
472 return 1;
473 }
474
475
476 /*
477 * dev_decxmi_init():
478 */
479 void dev_decxmi_init(struct memory *mem, uint64_t baseaddr)
480 {
481 struct decxmi_data *d;
482
483 d = malloc(sizeof(struct decxmi_data));
484 if (d == NULL) {
485 fprintf(stderr, "out of memory\n");
486 exit(1);
487 }
488 memset(d, 0, sizeof(struct decxmi_data));
489
490 memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH,
491 dev_decxmi_access, d, MEM_DEFAULT, NULL);
492 }
493

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