/[gxemul]/trunk/src/devices/dev_dec5800.c
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Contents of /trunk/src/devices/dev_dec5800.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 11878 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_dec5800.c,v 1.18 2006/01/01 13:17:16 debug Exp $
29 *
30 * Emulation of devices found in a DECsystem 58x0, where x is the number
31 * of CPUs in the system. (The CPU board is called KN5800 by Ultrix.)
32 *
33 * o) timers and misc stuff
34 * o) BI (Backplane Interconnect)
35 * o) CCA (Console Communication Area)
36 * o) XMI (Extended Memory Interconnect)
37 *
38 * TODO: This hardware is not very easy to find docs about.
39 * Perhaps VAX 6000/300 docs?
40 */
41
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <string.h>
45
46 #include "console.h"
47 #include "cpu.h"
48 #include "devices.h"
49 #include "machine.h"
50 #include "memory.h"
51 #include "misc.h"
52
53
54 /*
55 * dev_dec5800_tick():
56 */
57 void dev_dec5800_tick(struct cpu *cpu, void *extra)
58 {
59 struct dec5800_data *d = extra;
60
61 /* Timer interrupts? */
62 if (d->csr & 0x8000) {
63 debug("[ dec5800: timer interrupt! ]\n");
64
65 /* Set timer interrupt pending bit: */
66 d->csr |= 0x20000000;
67
68 cpu_interrupt(cpu, 3);
69 }
70 }
71
72
73 /*
74 * dev_dec5800_vectors_access():
75 */
76 DEVICE_ACCESS(dec5800_vectors)
77 {
78 uint64_t idata = 0, odata = 0;
79 struct dec5800_data *d = extra;
80
81 if (writeflag == MEM_WRITE)
82 idata = memory_readmax64(cpu, data, len);
83
84 if (writeflag == MEM_READ) {
85 /* TODO */
86 /* 0xfc = transmit interrupt, 0xf8 = receive interrupt,
87 0x80 = IPI */
88 odata = d->vector_0x50;
89 /* odata = 0xfc; */
90 debug("[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n",
91 (int)relative_addr, (int)odata);
92 } else {
93 d->vector_0x50 = idata;
94 debug("[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n",
95 (int)relative_addr, (int)idata);
96 }
97
98 if (writeflag == MEM_READ)
99 memory_writemax64(cpu, data, len, odata);
100
101 return 1;
102 }
103
104
105 /*
106 * dev_dec5800_access():
107 */
108 DEVICE_ACCESS(dec5800)
109 {
110 uint64_t idata = 0, odata = 0;
111 struct dec5800_data *d = extra;
112
113 if (writeflag == MEM_WRITE)
114 idata = memory_readmax64(cpu, data, len);
115
116 /* Lowest 4 bits of csr contain cpu id: */
117 d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf);
118
119 switch (relative_addr) {
120 case 0x0000: /* csr */
121 if (writeflag == MEM_READ) {
122 odata = d->csr;
123 odata ^= random() & 0x10000;
124 debug("[ dec5800: read from csr: 0x%08x ]\n",
125 (int)odata);
126 } else {
127 d->csr = idata;
128
129 /* Ack. timer interrupts: */
130 d->csr &= ~0x20000000;
131 cpu_interrupt_ack(cpu, 3);
132
133 debug("[ dec5800: write to csr: 0x%08x ]\n",
134 (int)idata);
135 }
136 break;
137 default:
138 if (writeflag==MEM_READ) {
139 debug("[ dec5800: read from 0x%08lx ]\n",
140 (long)relative_addr);
141 } else {
142 debug("[ dec5800: write to 0x%08lx: 0x%08x ]\n",
143 (long)relative_addr, (int)idata);
144 }
145 }
146
147 if (writeflag == MEM_READ)
148 memory_writemax64(cpu, data, len, odata);
149
150 return 1;
151 }
152
153
154 /*
155 * dev_dec5800_init():
156 */
157 struct dec5800_data *dev_dec5800_init(struct machine *machine,
158 struct memory *mem, uint64_t baseaddr)
159 {
160 struct dec5800_data *d;
161
162 d = malloc(sizeof(struct dec5800_data));
163 if (d == NULL) {
164 fprintf(stderr, "out of memory\n");
165 exit(1);
166 }
167 memset(d, 0, sizeof(struct dec5800_data));
168
169 memory_device_register(mem, "dec5800", baseaddr,
170 DEV_DEC5800_LENGTH, dev_dec5800_access, d, DM_DEFAULT, NULL);
171 memory_device_register(mem, "dec5800_vectors",
172 baseaddr + 0x30000000, 0x100, dev_dec5800_vectors_access,
173 d, DM_DEFAULT, NULL);
174 machine_add_tickfunction(machine, dev_dec5800_tick, d, 14);
175
176 return d;
177 }
178
179
180 /*****************************************************************************/
181
182
183 #include "bireg.h"
184
185 struct decbi_data {
186 int csr[NNODEBI];
187 };
188
189
190 /*
191 * dev_decbi_access():
192 */
193 DEVICE_ACCESS(decbi)
194 {
195 uint64_t idata = 0, odata = 0;
196 int node_nr;
197 struct decbi_data *d = extra;
198
199 if (writeflag == MEM_WRITE)
200 idata = memory_readmax64(cpu, data, len);
201
202 relative_addr += BI_NODESIZE; /* HACK */
203
204 node_nr = relative_addr / BI_NODESIZE;
205 relative_addr &= (BI_NODESIZE - 1);
206
207 /* TODO: This "1" here is the max node number in actual use. */
208 if (node_nr > 1 || node_nr >= NNODEBI)
209 return 0;
210
211 switch (relative_addr) {
212 case BIREG_DTYPE:
213 if (writeflag==MEM_READ) {
214 /*
215 * This is a list of the devices in our BI slots:
216 */
217 switch (node_nr) {
218 case 1: odata = BIDT_KDB50; break; /* Disk */
219 /* case 2: odata = BIDT_DEBNA; break; */
220 /* BIDT_DEBNA = Ethernet */
221 /* case 3: odata = BIDT_MS820; break; */
222 /* BIDT_MS820 = Memory */
223 default:
224 /* No device. */
225 odata = 0;
226 }
227
228 debug("[ decbi: (node %i) read from BIREG_DTYPE:"
229 " 0x%x ]\n", node_nr, (int)odata);
230 } else {
231 debug("[ decbi: (node %i) attempt to write to "
232 "BIREG_DTYPE: 0x%08x ]\n", node_nr, (int)idata);
233 }
234 break;
235 case BIREG_VAXBICSR:
236 if (writeflag==MEM_READ) {
237 odata = (d->csr[node_nr] & ~BICSR_NODEMASK) | node_nr;
238 debug("[ decbi: (node %i) read from BIREG_"
239 "VAXBICSR: 0x%x ]\n", node_nr, (int)odata);
240 } else {
241 d->csr[node_nr] = idata;
242 debug("[ decbi: (node %i) attempt to write to "
243 "BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (int)idata);
244 }
245 break;
246 case 0xf4:
247 if (writeflag==MEM_READ) {
248 odata = 0xffff; /* ? */
249 debug("[ decbi: (node %i) read from 0xf4: "
250 "0x%x ]\n", node_nr, (int)odata);
251 } else {
252 debug("[ decbi: (node %i) attempt to write "
253 "to 0xf4: 0x%08x ]\n", node_nr, (int)idata);
254 }
255 break;
256 default:
257 if (writeflag==MEM_READ) {
258 debug("[ decbi: (node %i) read from unimplemented "
259 "0x%08lx ]\n", node_nr, (long)relative_addr,
260 (int)odata);
261 } else {
262 debug("[ decbi: (node %i) write to unimplemented "
263 "0x%08lx: 0x%08x ]\n", node_nr,
264 (long)relative_addr, (int)idata);
265 }
266 }
267
268 if (writeflag == MEM_READ)
269 memory_writemax64(cpu, data, len, odata);
270
271 return 1;
272 }
273
274
275 /*
276 * dev_decbi_init():
277 */
278 void dev_decbi_init(struct memory *mem, uint64_t baseaddr)
279 {
280 struct decbi_data *d;
281
282 d = malloc(sizeof(struct decbi_data));
283 if (d == NULL) {
284 fprintf(stderr, "out of memory\n");
285 exit(1);
286 }
287 memset(d, 0, sizeof(struct decbi_data));
288
289 memory_device_register(mem, "decbi", baseaddr + 0x2000,
290 DEV_DECBI_LENGTH - 0x2000, dev_decbi_access, d, DM_DEFAULT, NULL);
291 }
292
293
294 /*****************************************************************************/
295
296
297 /*
298 * CCA, "Console Communication Area" for a DEC 5800 SMP system.
299 */
300
301 struct deccca_data {
302 int dummy;
303 };
304
305
306 /*
307 * dev_deccca_access():
308 */
309 DEVICE_ACCESS(deccca)
310 {
311 uint64_t idata = 0, odata = 0;
312 /* struct deccca_data *d = extra; */
313
314 if (writeflag == MEM_WRITE)
315 idata = memory_readmax64(cpu, data, len);
316
317 switch (relative_addr) {
318 case 6:
319 case 7:
320 /* CCA "ID" bytes? These must be here, or Ultrix complains. */
321 if (writeflag == MEM_READ)
322 odata = 67;
323 break;
324 case 8:
325 if (writeflag == MEM_READ)
326 odata = cpu->machine->ncpus;
327 break;
328 case 20:
329 if (writeflag == MEM_READ)
330 odata = (1 << cpu->machine->ncpus) - 1;
331 /* one bit for each cpu */
332 break;
333 case 28:
334 if (writeflag == MEM_READ)
335 odata = (1 << cpu->machine->ncpus) - 1;
336 /* one bit for each enabled(?) cpu */
337 break;
338 default:
339 if (writeflag==MEM_READ) {
340 debug("[ deccca: read from 0x%08lx ]\n",
341 (long)relative_addr);
342 } else {
343 debug("[ deccca: write to 0x%08lx: 0x%08x ]\n",
344 (long)relative_addr, (int)idata);
345 }
346 }
347
348 if (writeflag == MEM_READ)
349 memory_writemax64(cpu, data, len, odata);
350
351 return 1;
352 }
353
354
355 /*
356 * dev_deccca_init():
357 */
358 void dev_deccca_init(struct memory *mem, uint64_t baseaddr)
359 {
360 struct deccca_data *d;
361
362 d = malloc(sizeof(struct deccca_data));
363 if (d == NULL) {
364 fprintf(stderr, "out of memory\n");
365 exit(1);
366 }
367 memset(d, 0, sizeof(struct deccca_data));
368
369 memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH,
370 dev_deccca_access, d, DM_DEFAULT, NULL);
371 }
372
373
374 /*****************************************************************************/
375
376
377 /*
378 * DEC 5800 XMI (this has to do with SMP...)
379 */
380
381 #include "xmireg.h"
382
383 struct decxmi_data {
384 uint32_t reg_0xc[NNODEXMI];
385 };
386
387
388 /*
389 * dev_decxmi_access():
390 */
391 DEVICE_ACCESS(decxmi)
392 {
393 uint64_t idata = 0, odata = 0;
394 int node_nr;
395 struct decxmi_data *d = extra;
396
397 if (writeflag == MEM_WRITE)
398 idata = memory_readmax64(cpu, data, len);
399
400 node_nr = relative_addr / XMI_NODESIZE;
401 relative_addr &= (XMI_NODESIZE - 1);
402
403 if (node_nr >= cpu->machine->ncpus + 1 || node_nr >= NNODEXMI)
404 return 0;
405
406 switch (relative_addr) {
407 case XMI_TYPE:
408 if (writeflag == MEM_READ) {
409 /*
410 * The first node is an XMI->BI adapter node, and then
411 * there are n CPU nodes.
412 */
413 odata = XMIDT_ISIS;
414 if (node_nr == 0)
415 odata = XMIDT_DWMBA;
416
417 debug("[ decxmi: (node %i) read from XMI_TYPE: "
418 "0x%08x ]\n", node_nr, (int)odata);
419 } else
420 debug("[ decxmi: (node %i) write to XMI_TYPE: "
421 "0x%08x ]\n", node_nr, (int)idata);
422 break;
423 case XMI_BUSERR:
424 if (writeflag == MEM_READ) {
425 odata = 0;
426 debug("[ decxmi: (node %i) read from XMI_BUSERR: "
427 "0x%08x ]\n", node_nr, (int)odata);
428 } else
429 debug("[ decxmi: (node %i) write to XMI_BUSERR: "
430 "0x%08x ]\n", node_nr, (int)idata);
431 break;
432 case XMI_FAIL:
433 if (writeflag == MEM_READ) {
434 odata = 0;
435 debug("[ decxmi: (node %i) read from XMI_FAIL: "
436 "0x%08x ]\n", node_nr, (int)odata);
437 } else
438 debug("[ decxmi: (node %i) write to XMI_FAIL: "
439 "0x%08x ]\n", node_nr, (int)idata);
440 break;
441 case 0xc:
442 if (writeflag == MEM_READ) {
443 odata = d->reg_0xc[node_nr];
444 debug("[ decxmi: (node %i) read from REG 0xC: "
445 "0x%08x ]\n", node_nr, (int)odata);
446 } else {
447 d->reg_0xc[node_nr] = idata;
448 debug("[ decxmi: (node %i) write to REG 0xC: "
449 "0x%08x ]\n", node_nr, (int)idata);
450 }
451 break;
452 default:
453 if (writeflag==MEM_READ) {
454 debug("[ decxmi: (node %i) read from unimplemented "
455 "0x%08lx ]\n", node_nr, (long)relative_addr,
456 (int)odata);
457 } else {
458 debug("[ decxmi: (node %i) write to unimplemented "
459 "0x%08lx: 0x%08x ]\n", node_nr,
460 (long)relative_addr, (int)idata);
461 }
462 }
463
464 if (writeflag == MEM_READ)
465 memory_writemax64(cpu, data, len, odata);
466
467 return 1;
468 }
469
470
471 /*
472 * dev_decxmi_init():
473 */
474 void dev_decxmi_init(struct memory *mem, uint64_t baseaddr)
475 {
476 struct decxmi_data *d;
477
478 d = malloc(sizeof(struct decxmi_data));
479 if (d == NULL) {
480 fprintf(stderr, "out of memory\n");
481 exit(1);
482 }
483 memset(d, 0, sizeof(struct decxmi_data));
484
485 memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH,
486 dev_decxmi_access, d, DM_DEFAULT, NULL);
487 }
488

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