/[gxemul]/trunk/src/devices/dev_dec5800.c
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Annotation of /trunk/src/devices/dev_dec5800.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 12875 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 dpavlin 4 /*
2 dpavlin 34 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: dev_dec5800.c,v 1.23 2007/06/15 18:44:19 debug Exp $
29     *
30     * COMMENT: DECsystem 58x0 devices
31     *
32 dpavlin 4 * Emulation of devices found in a DECsystem 58x0, where x is the number
33     * of CPUs in the system. (The CPU board is called KN5800 by Ultrix.)
34     *
35     * o) timers and misc stuff
36     * o) BI (Backplane Interconnect)
37     * o) CCA (Console Communication Area)
38     * o) XMI (Extended Memory Interconnect)
39     *
40     * TODO: This hardware is not very easy to find docs about.
41     * Perhaps VAX 6000/300 docs?
42     */
43    
44     #include <stdio.h>
45     #include <stdlib.h>
46     #include <string.h>
47    
48     #include "console.h"
49     #include "cpu.h"
50 dpavlin 34 #include "device.h"
51 dpavlin 4 #include "devices.h"
52 dpavlin 34 #include "interrupt.h"
53 dpavlin 4 #include "machine.h"
54     #include "memory.h"
55     #include "misc.h"
56    
57    
58 dpavlin 34 #define DEV_DEC5800_LENGTH 0x1000 /* TODO */
59    
60     struct dec5800_data {
61     uint32_t csr;
62     struct interrupt cpu_irq;
63    
64     uint32_t vector_0x50;
65    
66     struct interrupt timer_irq;
67     };
68    
69    
70     void dec5800_interrupt_assert(struct interrupt *interrupt)
71 dpavlin 4 {
72 dpavlin 34 struct dec5800_data *d = interrupt->extra;
73     d->csr |= (1 << interrupt->line);
74     if (d->csr & 0x10000000)
75     INTERRUPT_ASSERT(d->cpu_irq);
76     }
77     void dec5800_interrupt_deassert(struct interrupt *interrupt)
78     {
79     struct dec5800_data *d = interrupt->extra;
80     d->csr &= ~(1 << interrupt->line);
81     if (!(d->csr & 0x10000000))
82     INTERRUPT_DEASSERT(d->cpu_irq);
83     }
84    
85    
86     DEVICE_TICK(dec5800)
87     {
88 dpavlin 4 struct dec5800_data *d = extra;
89    
90     /* Timer interrupts? */
91     if (d->csr & 0x8000) {
92     debug("[ dec5800: timer interrupt! ]\n");
93    
94     /* Set timer interrupt pending bit: */
95     d->csr |= 0x20000000;
96    
97 dpavlin 34 INTERRUPT_ASSERT(d->timer_irq);
98 dpavlin 4 }
99     }
100    
101    
102 dpavlin 22 DEVICE_ACCESS(dec5800_vectors)
103 dpavlin 4 {
104     uint64_t idata = 0, odata = 0;
105     struct dec5800_data *d = extra;
106    
107 dpavlin 18 if (writeflag == MEM_WRITE)
108     idata = memory_readmax64(cpu, data, len);
109 dpavlin 4
110     if (writeflag == MEM_READ) {
111     /* TODO */
112     /* 0xfc = transmit interrupt, 0xf8 = receive interrupt,
113     0x80 = IPI */
114     odata = d->vector_0x50;
115     /* odata = 0xfc; */
116     debug("[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n",
117     (int)relative_addr, (int)odata);
118     } else {
119     d->vector_0x50 = idata;
120     debug("[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n",
121     (int)relative_addr, (int)idata);
122     }
123    
124     if (writeflag == MEM_READ)
125     memory_writemax64(cpu, data, len, odata);
126    
127     return 1;
128     }
129    
130    
131 dpavlin 22 DEVICE_ACCESS(dec5800)
132 dpavlin 4 {
133     uint64_t idata = 0, odata = 0;
134     struct dec5800_data *d = extra;
135    
136 dpavlin 18 if (writeflag == MEM_WRITE)
137     idata = memory_readmax64(cpu, data, len);
138 dpavlin 4
139     /* Lowest 4 bits of csr contain cpu id: */
140     d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf);
141    
142     switch (relative_addr) {
143     case 0x0000: /* csr */
144     if (writeflag == MEM_READ) {
145     odata = d->csr;
146     odata ^= random() & 0x10000;
147     debug("[ dec5800: read from csr: 0x%08x ]\n",
148     (int)odata);
149     } else {
150     d->csr = idata;
151    
152     /* Ack. timer interrupts: */
153     d->csr &= ~0x20000000;
154 dpavlin 34 INTERRUPT_DEASSERT(d->timer_irq);
155 dpavlin 4
156     debug("[ dec5800: write to csr: 0x%08x ]\n",
157     (int)idata);
158     }
159     break;
160     default:
161     if (writeflag==MEM_READ) {
162     debug("[ dec5800: read from 0x%08lx ]\n",
163     (long)relative_addr);
164     } else {
165     debug("[ dec5800: write to 0x%08lx: 0x%08x ]\n",
166     (long)relative_addr, (int)idata);
167     }
168     }
169    
170     if (writeflag == MEM_READ)
171     memory_writemax64(cpu, data, len, odata);
172    
173     return 1;
174     }
175    
176    
177 dpavlin 34 DEVINIT(dec5800)
178 dpavlin 4 {
179     struct dec5800_data *d;
180 dpavlin 34 char tmpstr[200];
181     int i;
182 dpavlin 4
183 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct dec5800_data)));
184 dpavlin 4 memset(d, 0, sizeof(struct dec5800_data));
185    
186 dpavlin 34 snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
187     INTERRUPT_CONNECT(tmpstr, d->cpu_irq);
188    
189     snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
190     INTERRUPT_CONNECT(tmpstr, d->timer_irq);
191    
192     /* Register 32 CSR interrupts, corresponding to bits in the CSR: */
193     for (i=0; i<32; i++) {
194     char n[200];
195     struct interrupt template;
196     snprintf(n, sizeof(n), "%s.dec5800.%i",
197     devinit->interrupt_path, i);
198     memset(&template, 0, sizeof(template));
199     template.line = i;
200     template.name = n;
201     template.extra = d;
202     template.interrupt_assert = dec5800_interrupt_assert;
203     template.interrupt_deassert = dec5800_interrupt_deassert;
204     interrupt_handler_register(&template);
205     }
206    
207     memory_device_register(devinit->machine->memory, "dec5800",
208     devinit->addr, DEV_DEC5800_LENGTH, dev_dec5800_access,
209 dpavlin 20 d, DM_DEFAULT, NULL);
210 dpavlin 34 memory_device_register(devinit->machine->memory, "dec5800_vectors",
211     devinit->addr + 0x30000000, 0x100, dev_dec5800_vectors_access,
212     d, DM_DEFAULT, NULL);
213     machine_add_tickfunction(devinit->machine, dev_dec5800_tick,
214 dpavlin 42 d, 14);
215 dpavlin 4
216 dpavlin 34 return 1;
217 dpavlin 4 }
218    
219    
220     /*****************************************************************************/
221    
222    
223     #include "bireg.h"
224    
225 dpavlin 34 /* 16 slots, 0x2000 bytes each */
226     #define DEV_DECBI_LENGTH 0x20000
227    
228 dpavlin 4 struct decbi_data {
229     int csr[NNODEBI];
230     };
231    
232    
233 dpavlin 22 DEVICE_ACCESS(decbi)
234 dpavlin 4 {
235     uint64_t idata = 0, odata = 0;
236     int node_nr;
237     struct decbi_data *d = extra;
238    
239 dpavlin 18 if (writeflag == MEM_WRITE)
240     idata = memory_readmax64(cpu, data, len);
241 dpavlin 4
242     relative_addr += BI_NODESIZE; /* HACK */
243    
244     node_nr = relative_addr / BI_NODESIZE;
245     relative_addr &= (BI_NODESIZE - 1);
246    
247     /* TODO: This "1" here is the max node number in actual use. */
248     if (node_nr > 1 || node_nr >= NNODEBI)
249     return 0;
250    
251     switch (relative_addr) {
252     case BIREG_DTYPE:
253     if (writeflag==MEM_READ) {
254     /*
255     * This is a list of the devices in our BI slots:
256     */
257     switch (node_nr) {
258     case 1: odata = BIDT_KDB50; break; /* Disk */
259     /* case 2: odata = BIDT_DEBNA; break; */
260     /* BIDT_DEBNA = Ethernet */
261     /* case 3: odata = BIDT_MS820; break; */
262     /* BIDT_MS820 = Memory */
263     default:
264     /* No device. */
265     odata = 0;
266     }
267    
268     debug("[ decbi: (node %i) read from BIREG_DTYPE:"
269     " 0x%x ]\n", node_nr, (int)odata);
270     } else {
271     debug("[ decbi: (node %i) attempt to write to "
272     "BIREG_DTYPE: 0x%08x ]\n", node_nr, (int)idata);
273     }
274     break;
275     case BIREG_VAXBICSR:
276     if (writeflag==MEM_READ) {
277     odata = (d->csr[node_nr] & ~BICSR_NODEMASK) | node_nr;
278     debug("[ decbi: (node %i) read from BIREG_"
279     "VAXBICSR: 0x%x ]\n", node_nr, (int)odata);
280     } else {
281     d->csr[node_nr] = idata;
282     debug("[ decbi: (node %i) attempt to write to "
283     "BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (int)idata);
284     }
285     break;
286     case 0xf4:
287     if (writeflag==MEM_READ) {
288     odata = 0xffff; /* ? */
289     debug("[ decbi: (node %i) read from 0xf4: "
290     "0x%x ]\n", node_nr, (int)odata);
291     } else {
292     debug("[ decbi: (node %i) attempt to write "
293     "to 0xf4: 0x%08x ]\n", node_nr, (int)idata);
294     }
295     break;
296     default:
297     if (writeflag==MEM_READ) {
298     debug("[ decbi: (node %i) read from unimplemented "
299     "0x%08lx ]\n", node_nr, (long)relative_addr,
300     (int)odata);
301     } else {
302     debug("[ decbi: (node %i) write to unimplemented "
303     "0x%08lx: 0x%08x ]\n", node_nr,
304     (long)relative_addr, (int)idata);
305     }
306     }
307    
308     if (writeflag == MEM_READ)
309     memory_writemax64(cpu, data, len, odata);
310    
311     return 1;
312     }
313    
314    
315 dpavlin 34 DEVINIT(decbi)
316 dpavlin 4 {
317     struct decbi_data *d;
318    
319 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct decbi_data)));
320 dpavlin 4 memset(d, 0, sizeof(struct decbi_data));
321    
322 dpavlin 34 memory_device_register(devinit->machine->memory, "decbi",
323     devinit->addr + 0x2000, DEV_DECBI_LENGTH - 0x2000,
324     dev_decbi_access, d, DM_DEFAULT, NULL);
325    
326     return 1;
327 dpavlin 4 }
328    
329    
330     /*****************************************************************************/
331    
332    
333     /*
334     * CCA, "Console Communication Area" for a DEC 5800 SMP system.
335     */
336    
337     struct deccca_data {
338     int dummy;
339     };
340    
341    
342 dpavlin 22 DEVICE_ACCESS(deccca)
343 dpavlin 4 {
344     uint64_t idata = 0, odata = 0;
345     /* struct deccca_data *d = extra; */
346    
347 dpavlin 18 if (writeflag == MEM_WRITE)
348     idata = memory_readmax64(cpu, data, len);
349 dpavlin 4
350     switch (relative_addr) {
351     case 6:
352     case 7:
353     /* CCA "ID" bytes? These must be here, or Ultrix complains. */
354     if (writeflag == MEM_READ)
355     odata = 67;
356     break;
357     case 8:
358     if (writeflag == MEM_READ)
359     odata = cpu->machine->ncpus;
360     break;
361     case 20:
362     if (writeflag == MEM_READ)
363     odata = (1 << cpu->machine->ncpus) - 1;
364     /* one bit for each cpu */
365     break;
366     case 28:
367     if (writeflag == MEM_READ)
368     odata = (1 << cpu->machine->ncpus) - 1;
369     /* one bit for each enabled(?) cpu */
370     break;
371     default:
372     if (writeflag==MEM_READ) {
373     debug("[ deccca: read from 0x%08lx ]\n",
374     (long)relative_addr);
375     } else {
376     debug("[ deccca: write to 0x%08lx: 0x%08x ]\n",
377     (long)relative_addr, (int)idata);
378     }
379     }
380    
381     if (writeflag == MEM_READ)
382     memory_writemax64(cpu, data, len, odata);
383    
384     return 1;
385     }
386    
387    
388     /*
389     * dev_deccca_init():
390     */
391     void dev_deccca_init(struct memory *mem, uint64_t baseaddr)
392     {
393     struct deccca_data *d;
394    
395 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct deccca_data)));
396 dpavlin 4 memset(d, 0, sizeof(struct deccca_data));
397    
398     memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH,
399 dpavlin 20 dev_deccca_access, d, DM_DEFAULT, NULL);
400 dpavlin 4 }
401    
402    
403     /*****************************************************************************/
404    
405    
406     /*
407     * DEC 5800 XMI (this has to do with SMP...)
408     */
409    
410     #include "xmireg.h"
411    
412     struct decxmi_data {
413     uint32_t reg_0xc[NNODEXMI];
414     };
415    
416    
417     /*
418     * dev_decxmi_access():
419     */
420 dpavlin 22 DEVICE_ACCESS(decxmi)
421 dpavlin 4 {
422     uint64_t idata = 0, odata = 0;
423     int node_nr;
424     struct decxmi_data *d = extra;
425    
426 dpavlin 18 if (writeflag == MEM_WRITE)
427     idata = memory_readmax64(cpu, data, len);
428 dpavlin 4
429     node_nr = relative_addr / XMI_NODESIZE;
430     relative_addr &= (XMI_NODESIZE - 1);
431    
432     if (node_nr >= cpu->machine->ncpus + 1 || node_nr >= NNODEXMI)
433     return 0;
434    
435     switch (relative_addr) {
436     case XMI_TYPE:
437     if (writeflag == MEM_READ) {
438     /*
439     * The first node is an XMI->BI adapter node, and then
440     * there are n CPU nodes.
441     */
442     odata = XMIDT_ISIS;
443     if (node_nr == 0)
444     odata = XMIDT_DWMBA;
445    
446     debug("[ decxmi: (node %i) read from XMI_TYPE: "
447     "0x%08x ]\n", node_nr, (int)odata);
448     } else
449     debug("[ decxmi: (node %i) write to XMI_TYPE: "
450     "0x%08x ]\n", node_nr, (int)idata);
451     break;
452     case XMI_BUSERR:
453     if (writeflag == MEM_READ) {
454     odata = 0;
455     debug("[ decxmi: (node %i) read from XMI_BUSERR: "
456     "0x%08x ]\n", node_nr, (int)odata);
457     } else
458     debug("[ decxmi: (node %i) write to XMI_BUSERR: "
459     "0x%08x ]\n", node_nr, (int)idata);
460     break;
461     case XMI_FAIL:
462     if (writeflag == MEM_READ) {
463     odata = 0;
464     debug("[ decxmi: (node %i) read from XMI_FAIL: "
465     "0x%08x ]\n", node_nr, (int)odata);
466     } else
467     debug("[ decxmi: (node %i) write to XMI_FAIL: "
468     "0x%08x ]\n", node_nr, (int)idata);
469     break;
470     case 0xc:
471     if (writeflag == MEM_READ) {
472     odata = d->reg_0xc[node_nr];
473     debug("[ decxmi: (node %i) read from REG 0xC: "
474     "0x%08x ]\n", node_nr, (int)odata);
475     } else {
476     d->reg_0xc[node_nr] = idata;
477     debug("[ decxmi: (node %i) write to REG 0xC: "
478     "0x%08x ]\n", node_nr, (int)idata);
479     }
480     break;
481     default:
482     if (writeflag==MEM_READ) {
483     debug("[ decxmi: (node %i) read from unimplemented "
484     "0x%08lx ]\n", node_nr, (long)relative_addr,
485     (int)odata);
486     } else {
487     debug("[ decxmi: (node %i) write to unimplemented "
488     "0x%08lx: 0x%08x ]\n", node_nr,
489     (long)relative_addr, (int)idata);
490     }
491     }
492    
493     if (writeflag == MEM_READ)
494     memory_writemax64(cpu, data, len, odata);
495    
496     return 1;
497     }
498    
499    
500     /*
501     * dev_decxmi_init():
502     */
503     void dev_decxmi_init(struct memory *mem, uint64_t baseaddr)
504     {
505     struct decxmi_data *d;
506    
507 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct decxmi_data)));
508 dpavlin 4 memset(d, 0, sizeof(struct decxmi_data));
509    
510     memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH,
511 dpavlin 20 dev_decxmi_access, d, DM_DEFAULT, NULL);
512 dpavlin 4 }
513    

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