/[gxemul]/trunk/src/devices/dev_dec5800.c
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Contents of /trunk/src/devices/dev_dec5800.c

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 11883 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 /*
2 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_dec5800.c,v 1.19 2006/03/04 12:38:47 debug Exp $
29 *
30 * Emulation of devices found in a DECsystem 58x0, where x is the number
31 * of CPUs in the system. (The CPU board is called KN5800 by Ultrix.)
32 *
33 * o) timers and misc stuff
34 * o) BI (Backplane Interconnect)
35 * o) CCA (Console Communication Area)
36 * o) XMI (Extended Memory Interconnect)
37 *
38 * TODO: This hardware is not very easy to find docs about.
39 * Perhaps VAX 6000/300 docs?
40 */
41
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <string.h>
45
46 #include "console.h"
47 #include "cpu.h"
48 #include "devices.h"
49 #include "machine.h"
50 #include "memory.h"
51 #include "misc.h"
52
53
54 /*
55 * dev_dec5800_tick():
56 */
57 void dev_dec5800_tick(struct cpu *cpu, void *extra)
58 {
59 struct dec5800_data *d = extra;
60
61 /* Timer interrupts? */
62 if (d->csr & 0x8000) {
63 debug("[ dec5800: timer interrupt! ]\n");
64
65 /* Set timer interrupt pending bit: */
66 d->csr |= 0x20000000;
67
68 cpu_interrupt(cpu, 3);
69 }
70 }
71
72
73 /*
74 * dev_dec5800_vectors_access():
75 */
76 DEVICE_ACCESS(dec5800_vectors)
77 {
78 uint64_t idata = 0, odata = 0;
79 struct dec5800_data *d = extra;
80
81 if (writeflag == MEM_WRITE)
82 idata = memory_readmax64(cpu, data, len);
83
84 if (writeflag == MEM_READ) {
85 /* TODO */
86 /* 0xfc = transmit interrupt, 0xf8 = receive interrupt,
87 0x80 = IPI */
88 odata = d->vector_0x50;
89 /* odata = 0xfc; */
90 debug("[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n",
91 (int)relative_addr, (int)odata);
92 } else {
93 d->vector_0x50 = idata;
94 debug("[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n",
95 (int)relative_addr, (int)idata);
96 }
97
98 if (writeflag == MEM_READ)
99 memory_writemax64(cpu, data, len, odata);
100
101 return 1;
102 }
103
104
105 /*
106 * dev_dec5800_access():
107 */
108 DEVICE_ACCESS(dec5800)
109 {
110 uint64_t idata = 0, odata = 0;
111 struct dec5800_data *d = extra;
112
113 if (writeflag == MEM_WRITE)
114 idata = memory_readmax64(cpu, data, len);
115
116 /* Lowest 4 bits of csr contain cpu id: */
117 d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf);
118
119 switch (relative_addr) {
120 case 0x0000: /* csr */
121 if (writeflag == MEM_READ) {
122 odata = d->csr;
123 odata ^= random() & 0x10000;
124 debug("[ dec5800: read from csr: 0x%08x ]\n",
125 (int)odata);
126 } else {
127 d->csr = idata;
128
129 /* Ack. timer interrupts: */
130 d->csr &= ~0x20000000;
131 cpu_interrupt_ack(cpu, 3);
132
133 debug("[ dec5800: write to csr: 0x%08x ]\n",
134 (int)idata);
135 }
136 break;
137 default:
138 if (writeflag==MEM_READ) {
139 debug("[ dec5800: read from 0x%08lx ]\n",
140 (long)relative_addr);
141 } else {
142 debug("[ dec5800: write to 0x%08lx: 0x%08x ]\n",
143 (long)relative_addr, (int)idata);
144 }
145 }
146
147 if (writeflag == MEM_READ)
148 memory_writemax64(cpu, data, len, odata);
149
150 return 1;
151 }
152
153
154 /*
155 * dev_dec5800_init():
156 */
157 struct dec5800_data *dev_dec5800_init(struct machine *machine,
158 struct memory *mem, uint64_t baseaddr)
159 {
160 struct dec5800_data *d;
161
162 d = malloc(sizeof(struct dec5800_data));
163 if (d == NULL) {
164 fprintf(stderr, "out of memory\n");
165 exit(1);
166 }
167 memset(d, 0, sizeof(struct dec5800_data));
168
169 memory_device_register(mem, "dec5800", baseaddr,
170 DEV_DEC5800_LENGTH, dev_dec5800_access, d, DM_DEFAULT, NULL);
171 memory_device_register(mem, "dec5800_vectors",
172 baseaddr + 0x30000000, 0x100, dev_dec5800_vectors_access,
173 d, DM_DEFAULT, NULL);
174 machine_add_tickfunction(machine, dev_dec5800_tick, d, 14, 0.0);
175
176 return d;
177 }
178
179
180 /*****************************************************************************/
181
182
183 #include "bireg.h"
184
185 struct decbi_data {
186 int csr[NNODEBI];
187 };
188
189
190 /*
191 * dev_decbi_access():
192 */
193 DEVICE_ACCESS(decbi)
194 {
195 uint64_t idata = 0, odata = 0;
196 int node_nr;
197 struct decbi_data *d = extra;
198
199 if (writeflag == MEM_WRITE)
200 idata = memory_readmax64(cpu, data, len);
201
202 relative_addr += BI_NODESIZE; /* HACK */
203
204 node_nr = relative_addr / BI_NODESIZE;
205 relative_addr &= (BI_NODESIZE - 1);
206
207 /* TODO: This "1" here is the max node number in actual use. */
208 if (node_nr > 1 || node_nr >= NNODEBI)
209 return 0;
210
211 switch (relative_addr) {
212 case BIREG_DTYPE:
213 if (writeflag==MEM_READ) {
214 /*
215 * This is a list of the devices in our BI slots:
216 */
217 switch (node_nr) {
218 case 1: odata = BIDT_KDB50; break; /* Disk */
219 /* case 2: odata = BIDT_DEBNA; break; */
220 /* BIDT_DEBNA = Ethernet */
221 /* case 3: odata = BIDT_MS820; break; */
222 /* BIDT_MS820 = Memory */
223 default:
224 /* No device. */
225 odata = 0;
226 }
227
228 debug("[ decbi: (node %i) read from BIREG_DTYPE:"
229 " 0x%x ]\n", node_nr, (int)odata);
230 } else {
231 debug("[ decbi: (node %i) attempt to write to "
232 "BIREG_DTYPE: 0x%08x ]\n", node_nr, (int)idata);
233 }
234 break;
235 case BIREG_VAXBICSR:
236 if (writeflag==MEM_READ) {
237 odata = (d->csr[node_nr] & ~BICSR_NODEMASK) | node_nr;
238 debug("[ decbi: (node %i) read from BIREG_"
239 "VAXBICSR: 0x%x ]\n", node_nr, (int)odata);
240 } else {
241 d->csr[node_nr] = idata;
242 debug("[ decbi: (node %i) attempt to write to "
243 "BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (int)idata);
244 }
245 break;
246 case 0xf4:
247 if (writeflag==MEM_READ) {
248 odata = 0xffff; /* ? */
249 debug("[ decbi: (node %i) read from 0xf4: "
250 "0x%x ]\n", node_nr, (int)odata);
251 } else {
252 debug("[ decbi: (node %i) attempt to write "
253 "to 0xf4: 0x%08x ]\n", node_nr, (int)idata);
254 }
255 break;
256 default:
257 if (writeflag==MEM_READ) {
258 debug("[ decbi: (node %i) read from unimplemented "
259 "0x%08lx ]\n", node_nr, (long)relative_addr,
260 (int)odata);
261 } else {
262 debug("[ decbi: (node %i) write to unimplemented "
263 "0x%08lx: 0x%08x ]\n", node_nr,
264 (long)relative_addr, (int)idata);
265 }
266 }
267
268 if (writeflag == MEM_READ)
269 memory_writemax64(cpu, data, len, odata);
270
271 return 1;
272 }
273
274
275 /*
276 * dev_decbi_init():
277 */
278 void dev_decbi_init(struct memory *mem, uint64_t baseaddr)
279 {
280 struct decbi_data *d;
281
282 d = malloc(sizeof(struct decbi_data));
283 if (d == NULL) {
284 fprintf(stderr, "out of memory\n");
285 exit(1);
286 }
287 memset(d, 0, sizeof(struct decbi_data));
288
289 memory_device_register(mem, "decbi", baseaddr + 0x2000,
290 DEV_DECBI_LENGTH - 0x2000, dev_decbi_access, d, DM_DEFAULT, NULL);
291 }
292
293
294 /*****************************************************************************/
295
296
297 /*
298 * CCA, "Console Communication Area" for a DEC 5800 SMP system.
299 */
300
301 struct deccca_data {
302 int dummy;
303 };
304
305
306 /*
307 * dev_deccca_access():
308 */
309 DEVICE_ACCESS(deccca)
310 {
311 uint64_t idata = 0, odata = 0;
312 /* struct deccca_data *d = extra; */
313
314 if (writeflag == MEM_WRITE)
315 idata = memory_readmax64(cpu, data, len);
316
317 switch (relative_addr) {
318 case 6:
319 case 7:
320 /* CCA "ID" bytes? These must be here, or Ultrix complains. */
321 if (writeflag == MEM_READ)
322 odata = 67;
323 break;
324 case 8:
325 if (writeflag == MEM_READ)
326 odata = cpu->machine->ncpus;
327 break;
328 case 20:
329 if (writeflag == MEM_READ)
330 odata = (1 << cpu->machine->ncpus) - 1;
331 /* one bit for each cpu */
332 break;
333 case 28:
334 if (writeflag == MEM_READ)
335 odata = (1 << cpu->machine->ncpus) - 1;
336 /* one bit for each enabled(?) cpu */
337 break;
338 default:
339 if (writeflag==MEM_READ) {
340 debug("[ deccca: read from 0x%08lx ]\n",
341 (long)relative_addr);
342 } else {
343 debug("[ deccca: write to 0x%08lx: 0x%08x ]\n",
344 (long)relative_addr, (int)idata);
345 }
346 }
347
348 if (writeflag == MEM_READ)
349 memory_writemax64(cpu, data, len, odata);
350
351 return 1;
352 }
353
354
355 /*
356 * dev_deccca_init():
357 */
358 void dev_deccca_init(struct memory *mem, uint64_t baseaddr)
359 {
360 struct deccca_data *d;
361
362 d = malloc(sizeof(struct deccca_data));
363 if (d == NULL) {
364 fprintf(stderr, "out of memory\n");
365 exit(1);
366 }
367 memset(d, 0, sizeof(struct deccca_data));
368
369 memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH,
370 dev_deccca_access, d, DM_DEFAULT, NULL);
371 }
372
373
374 /*****************************************************************************/
375
376
377 /*
378 * DEC 5800 XMI (this has to do with SMP...)
379 */
380
381 #include "xmireg.h"
382
383 struct decxmi_data {
384 uint32_t reg_0xc[NNODEXMI];
385 };
386
387
388 /*
389 * dev_decxmi_access():
390 */
391 DEVICE_ACCESS(decxmi)
392 {
393 uint64_t idata = 0, odata = 0;
394 int node_nr;
395 struct decxmi_data *d = extra;
396
397 if (writeflag == MEM_WRITE)
398 idata = memory_readmax64(cpu, data, len);
399
400 node_nr = relative_addr / XMI_NODESIZE;
401 relative_addr &= (XMI_NODESIZE - 1);
402
403 if (node_nr >= cpu->machine->ncpus + 1 || node_nr >= NNODEXMI)
404 return 0;
405
406 switch (relative_addr) {
407 case XMI_TYPE:
408 if (writeflag == MEM_READ) {
409 /*
410 * The first node is an XMI->BI adapter node, and then
411 * there are n CPU nodes.
412 */
413 odata = XMIDT_ISIS;
414 if (node_nr == 0)
415 odata = XMIDT_DWMBA;
416
417 debug("[ decxmi: (node %i) read from XMI_TYPE: "
418 "0x%08x ]\n", node_nr, (int)odata);
419 } else
420 debug("[ decxmi: (node %i) write to XMI_TYPE: "
421 "0x%08x ]\n", node_nr, (int)idata);
422 break;
423 case XMI_BUSERR:
424 if (writeflag == MEM_READ) {
425 odata = 0;
426 debug("[ decxmi: (node %i) read from XMI_BUSERR: "
427 "0x%08x ]\n", node_nr, (int)odata);
428 } else
429 debug("[ decxmi: (node %i) write to XMI_BUSERR: "
430 "0x%08x ]\n", node_nr, (int)idata);
431 break;
432 case XMI_FAIL:
433 if (writeflag == MEM_READ) {
434 odata = 0;
435 debug("[ decxmi: (node %i) read from XMI_FAIL: "
436 "0x%08x ]\n", node_nr, (int)odata);
437 } else
438 debug("[ decxmi: (node %i) write to XMI_FAIL: "
439 "0x%08x ]\n", node_nr, (int)idata);
440 break;
441 case 0xc:
442 if (writeflag == MEM_READ) {
443 odata = d->reg_0xc[node_nr];
444 debug("[ decxmi: (node %i) read from REG 0xC: "
445 "0x%08x ]\n", node_nr, (int)odata);
446 } else {
447 d->reg_0xc[node_nr] = idata;
448 debug("[ decxmi: (node %i) write to REG 0xC: "
449 "0x%08x ]\n", node_nr, (int)idata);
450 }
451 break;
452 default:
453 if (writeflag==MEM_READ) {
454 debug("[ decxmi: (node %i) read from unimplemented "
455 "0x%08lx ]\n", node_nr, (long)relative_addr,
456 (int)odata);
457 } else {
458 debug("[ decxmi: (node %i) write to unimplemented "
459 "0x%08lx: 0x%08x ]\n", node_nr,
460 (long)relative_addr, (int)idata);
461 }
462 }
463
464 if (writeflag == MEM_READ)
465 memory_writemax64(cpu, data, len, odata);
466
467 return 1;
468 }
469
470
471 /*
472 * dev_decxmi_init():
473 */
474 void dev_decxmi_init(struct memory *mem, uint64_t baseaddr)
475 {
476 struct decxmi_data *d;
477
478 d = malloc(sizeof(struct decxmi_data));
479 if (d == NULL) {
480 fprintf(stderr, "out of memory\n");
481 exit(1);
482 }
483 memset(d, 0, sizeof(struct decxmi_data));
484
485 memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH,
486 dev_decxmi_access, d, DM_DEFAULT, NULL);
487 }
488

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