1 |
/* |
/* |
2 |
* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_dec5800.c,v 1.17 2005/11/13 00:14:08 debug Exp $ |
* $Id: dev_dec5800.c,v 1.23 2007/06/15 18:44:19 debug Exp $ |
29 |
* |
* |
30 |
|
* COMMENT: DECsystem 58x0 devices |
31 |
|
* |
32 |
* Emulation of devices found in a DECsystem 58x0, where x is the number |
* Emulation of devices found in a DECsystem 58x0, where x is the number |
33 |
* of CPUs in the system. (The CPU board is called KN5800 by Ultrix.) |
* of CPUs in the system. (The CPU board is called KN5800 by Ultrix.) |
34 |
* |
* |
47 |
|
|
48 |
#include "console.h" |
#include "console.h" |
49 |
#include "cpu.h" |
#include "cpu.h" |
50 |
|
#include "device.h" |
51 |
#include "devices.h" |
#include "devices.h" |
52 |
|
#include "interrupt.h" |
53 |
#include "machine.h" |
#include "machine.h" |
54 |
#include "memory.h" |
#include "memory.h" |
55 |
#include "misc.h" |
#include "misc.h" |
56 |
|
|
57 |
|
|
58 |
/* |
#define DEV_DEC5800_LENGTH 0x1000 /* TODO */ |
59 |
* dev_dec5800_tick(): |
|
60 |
*/ |
struct dec5800_data { |
61 |
void dev_dec5800_tick(struct cpu *cpu, void *extra) |
uint32_t csr; |
62 |
|
struct interrupt cpu_irq; |
63 |
|
|
64 |
|
uint32_t vector_0x50; |
65 |
|
|
66 |
|
struct interrupt timer_irq; |
67 |
|
}; |
68 |
|
|
69 |
|
|
70 |
|
void dec5800_interrupt_assert(struct interrupt *interrupt) |
71 |
|
{ |
72 |
|
struct dec5800_data *d = interrupt->extra; |
73 |
|
d->csr |= (1 << interrupt->line); |
74 |
|
if (d->csr & 0x10000000) |
75 |
|
INTERRUPT_ASSERT(d->cpu_irq); |
76 |
|
} |
77 |
|
void dec5800_interrupt_deassert(struct interrupt *interrupt) |
78 |
|
{ |
79 |
|
struct dec5800_data *d = interrupt->extra; |
80 |
|
d->csr &= ~(1 << interrupt->line); |
81 |
|
if (!(d->csr & 0x10000000)) |
82 |
|
INTERRUPT_DEASSERT(d->cpu_irq); |
83 |
|
} |
84 |
|
|
85 |
|
|
86 |
|
DEVICE_TICK(dec5800) |
87 |
{ |
{ |
88 |
struct dec5800_data *d = extra; |
struct dec5800_data *d = extra; |
89 |
|
|
94 |
/* Set timer interrupt pending bit: */ |
/* Set timer interrupt pending bit: */ |
95 |
d->csr |= 0x20000000; |
d->csr |= 0x20000000; |
96 |
|
|
97 |
cpu_interrupt(cpu, 3); |
INTERRUPT_ASSERT(d->timer_irq); |
98 |
} |
} |
99 |
} |
} |
100 |
|
|
101 |
|
|
102 |
/* |
DEVICE_ACCESS(dec5800_vectors) |
|
* dev_dec5800_vectors_access(): |
|
|
*/ |
|
|
int dev_dec5800_vectors_access(struct cpu *cpu, struct memory *mem, |
|
|
uint64_t relative_addr, unsigned char *data, size_t len, |
|
|
int writeflag, void *extra) |
|
103 |
{ |
{ |
104 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
105 |
struct dec5800_data *d = extra; |
struct dec5800_data *d = extra; |
128 |
} |
} |
129 |
|
|
130 |
|
|
131 |
/* |
DEVICE_ACCESS(dec5800) |
|
* dev_dec5800_access(): |
|
|
*/ |
|
|
int dev_dec5800_access(struct cpu *cpu, struct memory *mem, |
|
|
uint64_t relative_addr, unsigned char *data, size_t len, |
|
|
int writeflag, void *extra) |
|
132 |
{ |
{ |
133 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
134 |
struct dec5800_data *d = extra; |
struct dec5800_data *d = extra; |
151 |
|
|
152 |
/* Ack. timer interrupts: */ |
/* Ack. timer interrupts: */ |
153 |
d->csr &= ~0x20000000; |
d->csr &= ~0x20000000; |
154 |
cpu_interrupt_ack(cpu, 3); |
INTERRUPT_DEASSERT(d->timer_irq); |
155 |
|
|
156 |
debug("[ dec5800: write to csr: 0x%08x ]\n", |
debug("[ dec5800: write to csr: 0x%08x ]\n", |
157 |
(int)idata); |
(int)idata); |
174 |
} |
} |
175 |
|
|
176 |
|
|
177 |
/* |
DEVINIT(dec5800) |
|
* dev_dec5800_init(): |
|
|
*/ |
|
|
struct dec5800_data *dev_dec5800_init(struct machine *machine, |
|
|
struct memory *mem, uint64_t baseaddr) |
|
178 |
{ |
{ |
179 |
struct dec5800_data *d; |
struct dec5800_data *d; |
180 |
|
char tmpstr[200]; |
181 |
|
int i; |
182 |
|
|
183 |
d = malloc(sizeof(struct dec5800_data)); |
CHECK_ALLOCATION(d = malloc(sizeof(struct dec5800_data))); |
|
if (d == NULL) { |
|
|
fprintf(stderr, "out of memory\n"); |
|
|
exit(1); |
|
|
} |
|
184 |
memset(d, 0, sizeof(struct dec5800_data)); |
memset(d, 0, sizeof(struct dec5800_data)); |
185 |
|
|
186 |
memory_device_register(mem, "dec5800", baseaddr, |
snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path); |
187 |
DEV_DEC5800_LENGTH, dev_dec5800_access, d, DM_DEFAULT, NULL); |
INTERRUPT_CONNECT(tmpstr, d->cpu_irq); |
188 |
memory_device_register(mem, "dec5800_vectors", |
|
189 |
baseaddr + 0x30000000, 0x100, dev_dec5800_vectors_access, |
snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path); |
190 |
|
INTERRUPT_CONNECT(tmpstr, d->timer_irq); |
191 |
|
|
192 |
|
/* Register 32 CSR interrupts, corresponding to bits in the CSR: */ |
193 |
|
for (i=0; i<32; i++) { |
194 |
|
char n[200]; |
195 |
|
struct interrupt template; |
196 |
|
snprintf(n, sizeof(n), "%s.dec5800.%i", |
197 |
|
devinit->interrupt_path, i); |
198 |
|
memset(&template, 0, sizeof(template)); |
199 |
|
template.line = i; |
200 |
|
template.name = n; |
201 |
|
template.extra = d; |
202 |
|
template.interrupt_assert = dec5800_interrupt_assert; |
203 |
|
template.interrupt_deassert = dec5800_interrupt_deassert; |
204 |
|
interrupt_handler_register(&template); |
205 |
|
} |
206 |
|
|
207 |
|
memory_device_register(devinit->machine->memory, "dec5800", |
208 |
|
devinit->addr, DEV_DEC5800_LENGTH, dev_dec5800_access, |
209 |
|
d, DM_DEFAULT, NULL); |
210 |
|
memory_device_register(devinit->machine->memory, "dec5800_vectors", |
211 |
|
devinit->addr + 0x30000000, 0x100, dev_dec5800_vectors_access, |
212 |
d, DM_DEFAULT, NULL); |
d, DM_DEFAULT, NULL); |
213 |
machine_add_tickfunction(machine, dev_dec5800_tick, d, 14); |
machine_add_tickfunction(devinit->machine, dev_dec5800_tick, |
214 |
|
d, 14); |
215 |
|
|
216 |
return d; |
return 1; |
217 |
} |
} |
218 |
|
|
219 |
|
|
222 |
|
|
223 |
#include "bireg.h" |
#include "bireg.h" |
224 |
|
|
225 |
|
/* 16 slots, 0x2000 bytes each */ |
226 |
|
#define DEV_DECBI_LENGTH 0x20000 |
227 |
|
|
228 |
struct decbi_data { |
struct decbi_data { |
229 |
int csr[NNODEBI]; |
int csr[NNODEBI]; |
230 |
}; |
}; |
231 |
|
|
232 |
|
|
233 |
/* |
DEVICE_ACCESS(decbi) |
|
* dev_decbi_access(): |
|
|
*/ |
|
|
int dev_decbi_access(struct cpu *cpu, struct memory *mem, |
|
|
uint64_t relative_addr, unsigned char *data, size_t len, |
|
|
int writeflag, void *extra) |
|
234 |
{ |
{ |
235 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
236 |
int node_nr; |
int node_nr; |
312 |
} |
} |
313 |
|
|
314 |
|
|
315 |
/* |
DEVINIT(decbi) |
|
* dev_decbi_init(): |
|
|
*/ |
|
|
void dev_decbi_init(struct memory *mem, uint64_t baseaddr) |
|
316 |
{ |
{ |
317 |
struct decbi_data *d; |
struct decbi_data *d; |
318 |
|
|
319 |
d = malloc(sizeof(struct decbi_data)); |
CHECK_ALLOCATION(d = malloc(sizeof(struct decbi_data))); |
|
if (d == NULL) { |
|
|
fprintf(stderr, "out of memory\n"); |
|
|
exit(1); |
|
|
} |
|
320 |
memset(d, 0, sizeof(struct decbi_data)); |
memset(d, 0, sizeof(struct decbi_data)); |
321 |
|
|
322 |
memory_device_register(mem, "decbi", baseaddr + 0x2000, |
memory_device_register(devinit->machine->memory, "decbi", |
323 |
DEV_DECBI_LENGTH - 0x2000, dev_decbi_access, d, DM_DEFAULT, NULL); |
devinit->addr + 0x2000, DEV_DECBI_LENGTH - 0x2000, |
324 |
|
dev_decbi_access, d, DM_DEFAULT, NULL); |
325 |
|
|
326 |
|
return 1; |
327 |
} |
} |
328 |
|
|
329 |
|
|
339 |
}; |
}; |
340 |
|
|
341 |
|
|
342 |
/* |
DEVICE_ACCESS(deccca) |
|
* dev_deccca_access(): |
|
|
*/ |
|
|
int dev_deccca_access(struct cpu *cpu, struct memory *mem, |
|
|
uint64_t relative_addr, unsigned char *data, size_t len, |
|
|
int writeflag, void *extra) |
|
343 |
{ |
{ |
344 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
345 |
/* struct deccca_data *d = extra; */ |
/* struct deccca_data *d = extra; */ |
392 |
{ |
{ |
393 |
struct deccca_data *d; |
struct deccca_data *d; |
394 |
|
|
395 |
d = malloc(sizeof(struct deccca_data)); |
CHECK_ALLOCATION(d = malloc(sizeof(struct deccca_data))); |
|
if (d == NULL) { |
|
|
fprintf(stderr, "out of memory\n"); |
|
|
exit(1); |
|
|
} |
|
396 |
memset(d, 0, sizeof(struct deccca_data)); |
memset(d, 0, sizeof(struct deccca_data)); |
397 |
|
|
398 |
memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH, |
memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH, |
417 |
/* |
/* |
418 |
* dev_decxmi_access(): |
* dev_decxmi_access(): |
419 |
*/ |
*/ |
420 |
int dev_decxmi_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(decxmi) |
|
uint64_t relative_addr, unsigned char *data, size_t len, |
|
|
int writeflag, void *extra) |
|
421 |
{ |
{ |
422 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
423 |
int node_nr; |
int node_nr; |
504 |
{ |
{ |
505 |
struct decxmi_data *d; |
struct decxmi_data *d; |
506 |
|
|
507 |
d = malloc(sizeof(struct decxmi_data)); |
CHECK_ALLOCATION(d = malloc(sizeof(struct decxmi_data))); |
|
if (d == NULL) { |
|
|
fprintf(stderr, "out of memory\n"); |
|
|
exit(1); |
|
|
} |
|
508 |
memset(d, 0, sizeof(struct decxmi_data)); |
memset(d, 0, sizeof(struct decxmi_data)); |
509 |
|
|
510 |
memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH, |
memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH, |