/[gxemul]/trunk/src/devices/dev_dec5800.c
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revision 4 by dpavlin, Mon Oct 8 16:18:00 2007 UTC revision 34 by dpavlin, Mon Oct 8 16:21:17 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2007  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_dec5800.c,v 1.15 2005/02/22 06:26:10 debug Exp $   *  $Id: dev_dec5800.c,v 1.21 2007/01/28 00:41:16 debug Exp $
29   *     *  
30   *  Emulation of devices found in a DECsystem 58x0, where x is the number   *  Emulation of devices found in a DECsystem 58x0, where x is the number
31   *  of CPUs in the system. (The CPU board is called KN5800 by Ultrix.)   *  of CPUs in the system. (The CPU board is called KN5800 by Ultrix.)
# Line 45  Line 45 
45    
46  #include "console.h"  #include "console.h"
47  #include "cpu.h"  #include "cpu.h"
48    #include "device.h"
49  #include "devices.h"  #include "devices.h"
50    #include "interrupt.h"
51  #include "machine.h"  #include "machine.h"
52  #include "memory.h"  #include "memory.h"
53  #include "misc.h"  #include "misc.h"
54    
55    
56  /*  #define DEV_DEC5800_LENGTH              0x1000          /*  TODO  */
57   *  dev_dec5800_tick():  
58   */  struct dec5800_data {
59  void dev_dec5800_tick(struct cpu *cpu, void *extra)          uint32_t        csr;
60            struct interrupt cpu_irq;
61    
62            uint32_t        vector_0x50;
63    
64            struct interrupt timer_irq;
65    };
66    
67    
68    void dec5800_interrupt_assert(struct interrupt *interrupt)
69    {
70            struct dec5800_data *d = interrupt->extra;
71            d->csr |= (1 << interrupt->line);
72            if (d->csr & 0x10000000)
73                    INTERRUPT_ASSERT(d->cpu_irq);
74    }
75    void dec5800_interrupt_deassert(struct interrupt *interrupt)
76    {
77            struct dec5800_data *d = interrupt->extra;
78            d->csr &= ~(1 << interrupt->line);
79            if (!(d->csr & 0x10000000))
80                    INTERRUPT_DEASSERT(d->cpu_irq);
81    }
82    
83    
84    DEVICE_TICK(dec5800)
85  {  {
86          struct dec5800_data *d = extra;          struct dec5800_data *d = extra;
87    
# Line 65  void dev_dec5800_tick(struct cpu *cpu, v Line 92  void dev_dec5800_tick(struct cpu *cpu, v
92                  /*  Set timer interrupt pending bit:  */                  /*  Set timer interrupt pending bit:  */
93                  d->csr |= 0x20000000;                  d->csr |= 0x20000000;
94    
95                  cpu_interrupt(cpu, 3);                  INTERRUPT_ASSERT(d->timer_irq);
96          }          }
97  }  }
98    
99    
100  /*  DEVICE_ACCESS(dec5800_vectors)
  *  dev_dec5800_vectors_access():  
  */  
 int dev_dec5800_vectors_access(struct cpu *cpu, struct memory *mem,  
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
101  {  {
102          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
103          struct dec5800_data *d = extra;          struct dec5800_data *d = extra;
104    
105          idata = memory_readmax64(cpu, data, len);          if (writeflag == MEM_WRITE)
106                    idata = memory_readmax64(cpu, data, len);
107    
108          if (writeflag == MEM_READ) {          if (writeflag == MEM_READ) {
109                  /*  TODO  */                  /*  TODO  */
# Line 103  int dev_dec5800_vectors_access(struct cp Line 126  int dev_dec5800_vectors_access(struct cp
126  }  }
127    
128    
129  /*  DEVICE_ACCESS(dec5800)
  *  dev_dec5800_access():  
  */  
 int dev_dec5800_access(struct cpu *cpu, struct memory *mem,  
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
130  {  {
131          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
132          struct dec5800_data *d = extra;          struct dec5800_data *d = extra;
133    
134          idata = memory_readmax64(cpu, data, len);          if (writeflag == MEM_WRITE)
135                    idata = memory_readmax64(cpu, data, len);
136    
137          /*  Lowest 4 bits of csr contain cpu id:  */          /*  Lowest 4 bits of csr contain cpu id:  */
138          d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf);          d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf);
# Line 130  int dev_dec5800_access(struct cpu *cpu, Line 149  int dev_dec5800_access(struct cpu *cpu,
149    
150                          /*  Ack. timer interrupts:  */                          /*  Ack. timer interrupts:  */
151                          d->csr &= ~0x20000000;                          d->csr &= ~0x20000000;
152                          cpu_interrupt_ack(cpu, 3);                          INTERRUPT_DEASSERT(d->timer_irq);
153    
154                          debug("[ dec5800: write to csr: 0x%08x ]\n",                          debug("[ dec5800: write to csr: 0x%08x ]\n",
155                              (int)idata);                              (int)idata);
# Line 153  int dev_dec5800_access(struct cpu *cpu, Line 172  int dev_dec5800_access(struct cpu *cpu,
172  }  }
173    
174    
175  /*  DEVINIT(dec5800)
  *  dev_dec5800_init():  
  */  
 struct dec5800_data *dev_dec5800_init(struct machine *machine,  
         struct memory *mem, uint64_t baseaddr)  
176  {  {
177          struct dec5800_data *d;          struct dec5800_data *d;
178            char tmpstr[200];
179            int i;
180    
181          d = malloc(sizeof(struct dec5800_data));          d = malloc(sizeof(struct dec5800_data));
182          if (d == NULL) {          if (d == NULL) {
# Line 168  struct dec5800_data *dev_dec5800_init(st Line 185  struct dec5800_data *dev_dec5800_init(st
185          }          }
186          memset(d, 0, sizeof(struct dec5800_data));          memset(d, 0, sizeof(struct dec5800_data));
187    
188          memory_device_register(mem, "dec5800", baseaddr,          snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
189              DEV_DEC5800_LENGTH, dev_dec5800_access, d, MEM_DEFAULT, NULL);          INTERRUPT_CONNECT(tmpstr, d->cpu_irq);
         memory_device_register(mem, "dec5800_vectors",  
             baseaddr + 0x30000000, 0x100, dev_dec5800_vectors_access,  
             d, MEM_DEFAULT, NULL);  
         machine_add_tickfunction(machine, dev_dec5800_tick, d, 14);  
190    
191          return d;          snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
192            INTERRUPT_CONNECT(tmpstr, d->timer_irq);
193    
194            /*  Register 32 CSR interrupts, corresponding to bits in the CSR:  */
195            for (i=0; i<32; i++) {
196                    char n[200];
197                    struct interrupt template;
198                    snprintf(n, sizeof(n), "%s.dec5800.%i",
199                        devinit->interrupt_path, i);
200                    memset(&template, 0, sizeof(template));
201                    template.line = i;
202                    template.name = n;
203                    template.extra = d;
204                    template.interrupt_assert = dec5800_interrupt_assert;
205                    template.interrupt_deassert = dec5800_interrupt_deassert;
206                    interrupt_handler_register(&template);
207            }
208    
209            memory_device_register(devinit->machine->memory, "dec5800",
210                devinit->addr, DEV_DEC5800_LENGTH, dev_dec5800_access,
211                d, DM_DEFAULT, NULL);
212            memory_device_register(devinit->machine->memory, "dec5800_vectors",
213                devinit->addr + 0x30000000, 0x100, dev_dec5800_vectors_access,
214                d, DM_DEFAULT, NULL);
215            machine_add_tickfunction(devinit->machine, dev_dec5800_tick,
216                d, 14, 0.0);
217    
218            return 1;
219  }  }
220    
221    
# Line 184  struct dec5800_data *dev_dec5800_init(st Line 224  struct dec5800_data *dev_dec5800_init(st
224    
225  #include "bireg.h"  #include "bireg.h"
226    
227    /*  16 slots, 0x2000 bytes each  */
228    #define DEV_DECBI_LENGTH                0x20000
229    
230  struct decbi_data {  struct decbi_data {
231          int             csr[NNODEBI];          int             csr[NNODEBI];
232  };  };
233    
234    
235  /*  DEVICE_ACCESS(decbi)
  *  dev_decbi_access():  
  */  
 int dev_decbi_access(struct cpu *cpu, struct memory *mem,  
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
236  {  {
237          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
238          int node_nr;          int node_nr;
239          struct decbi_data *d = extra;          struct decbi_data *d = extra;
240    
241          idata = memory_readmax64(cpu, data, len);          if (writeflag == MEM_WRITE)
242                    idata = memory_readmax64(cpu, data, len);
243    
244          relative_addr += BI_NODESIZE;   /*  HACK  */          relative_addr += BI_NODESIZE;   /*  HACK  */
245    
# Line 275  int dev_decbi_access(struct cpu *cpu, st Line 314  int dev_decbi_access(struct cpu *cpu, st
314  }  }
315    
316    
317  /*  DEVINIT(decbi)
  *  dev_decbi_init():  
  */  
 void dev_decbi_init(struct memory *mem, uint64_t baseaddr)  
318  {  {
319          struct decbi_data *d;          struct decbi_data *d;
320    
# Line 289  void dev_decbi_init(struct memory *mem, Line 325  void dev_decbi_init(struct memory *mem,
325          }          }
326          memset(d, 0, sizeof(struct decbi_data));          memset(d, 0, sizeof(struct decbi_data));
327    
328          memory_device_register(mem, "decbi", baseaddr + 0x2000,          memory_device_register(devinit->machine->memory, "decbi",
329              DEV_DECBI_LENGTH - 0x2000, dev_decbi_access, d, MEM_DEFAULT, NULL);              devinit->addr + 0x2000, DEV_DECBI_LENGTH - 0x2000,
330                dev_decbi_access, d, DM_DEFAULT, NULL);
331    
332            return 1;
333  }  }
334    
335    
# Line 306  struct deccca_data { Line 345  struct deccca_data {
345  };  };
346    
347    
348  /*  DEVICE_ACCESS(deccca)
  *  dev_deccca_access():  
  */  
 int dev_deccca_access(struct cpu *cpu, struct memory *mem,  
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
349  {  {
350          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
351          /*  struct deccca_data *d = extra;  */          /*  struct deccca_data *d = extra;  */
352    
353          idata = memory_readmax64(cpu, data, len);          if (writeflag == MEM_WRITE)
354                    idata = memory_readmax64(cpu, data, len);
355    
356          switch (relative_addr) {          switch (relative_addr) {
357          case 6:          case 6:
# Line 371  void dev_deccca_init(struct memory *mem, Line 406  void dev_deccca_init(struct memory *mem,
406          memset(d, 0, sizeof(struct deccca_data));          memset(d, 0, sizeof(struct deccca_data));
407    
408          memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH,          memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH,
409              dev_deccca_access, d, MEM_DEFAULT, NULL);              dev_deccca_access, d, DM_DEFAULT, NULL);
410  }  }
411    
412    
# Line 392  struct decxmi_data { Line 427  struct decxmi_data {
427  /*  /*
428   *  dev_decxmi_access():   *  dev_decxmi_access():
429   */   */
430  int dev_decxmi_access(struct cpu *cpu, struct memory *mem,  DEVICE_ACCESS(decxmi)
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
431  {  {
432          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
433          int node_nr;          int node_nr;
434          struct decxmi_data *d = extra;          struct decxmi_data *d = extra;
435    
436          idata = memory_readmax64(cpu, data, len);          if (writeflag == MEM_WRITE)
437                    idata = memory_readmax64(cpu, data, len);
438    
439          node_nr = relative_addr / XMI_NODESIZE;          node_nr = relative_addr / XMI_NODESIZE;
440          relative_addr &= (XMI_NODESIZE - 1);          relative_addr &= (XMI_NODESIZE - 1);
# Line 488  void dev_decxmi_init(struct memory *mem, Line 522  void dev_decxmi_init(struct memory *mem,
522          memset(d, 0, sizeof(struct decxmi_data));          memset(d, 0, sizeof(struct decxmi_data));
523    
524          memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH,          memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH,
525              dev_decxmi_access, d, MEM_DEFAULT, NULL);              dev_decxmi_access, d, DM_DEFAULT, NULL);
526  }  }
527    
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