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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_dec5800.c,v 1.21 2007/01/28 00:41:16 debug Exp $ |
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* |
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* Emulation of devices found in a DECsystem 58x0, where x is the number |
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* of CPUs in the system. (The CPU board is called KN5800 by Ultrix.) |
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* |
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* o) timers and misc stuff |
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* o) BI (Backplane Interconnect) |
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* o) CCA (Console Communication Area) |
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* o) XMI (Extended Memory Interconnect) |
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* |
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* TODO: This hardware is not very easy to find docs about. |
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* Perhaps VAX 6000/300 docs? |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "console.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "devices.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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#define DEV_DEC5800_LENGTH 0x1000 /* TODO */ |
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|
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struct dec5800_data { |
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uint32_t csr; |
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struct interrupt cpu_irq; |
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|
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uint32_t vector_0x50; |
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|
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struct interrupt timer_irq; |
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}; |
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|
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|
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void dec5800_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct dec5800_data *d = interrupt->extra; |
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d->csr |= (1 << interrupt->line); |
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if (d->csr & 0x10000000) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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void dec5800_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct dec5800_data *d = interrupt->extra; |
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d->csr &= ~(1 << interrupt->line); |
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if (!(d->csr & 0x10000000)) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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} |
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|
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|
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DEVICE_TICK(dec5800) |
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{ |
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struct dec5800_data *d = extra; |
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|
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/* Timer interrupts? */ |
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if (d->csr & 0x8000) { |
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debug("[ dec5800: timer interrupt! ]\n"); |
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|
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/* Set timer interrupt pending bit: */ |
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d->csr |= 0x20000000; |
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|
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INTERRUPT_ASSERT(d->timer_irq); |
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} |
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} |
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|
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|
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DEVICE_ACCESS(dec5800_vectors) |
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{ |
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uint64_t idata = 0, odata = 0; |
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struct dec5800_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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if (writeflag == MEM_READ) { |
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/* TODO */ |
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/* 0xfc = transmit interrupt, 0xf8 = receive interrupt, |
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0x80 = IPI */ |
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odata = d->vector_0x50; |
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/* odata = 0xfc; */ |
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debug("[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n", |
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(int)relative_addr, (int)odata); |
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} else { |
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d->vector_0x50 = idata; |
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debug("[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n", |
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(int)relative_addr, (int)idata); |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVICE_ACCESS(dec5800) |
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{ |
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uint64_t idata = 0, odata = 0; |
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struct dec5800_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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/* Lowest 4 bits of csr contain cpu id: */ |
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d->csr = (d->csr & ~0xf) | (cpu->cpu_id & 0xf); |
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|
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switch (relative_addr) { |
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case 0x0000: /* csr */ |
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if (writeflag == MEM_READ) { |
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odata = d->csr; |
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odata ^= random() & 0x10000; |
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debug("[ dec5800: read from csr: 0x%08x ]\n", |
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(int)odata); |
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} else { |
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d->csr = idata; |
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|
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/* Ack. timer interrupts: */ |
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d->csr &= ~0x20000000; |
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INTERRUPT_DEASSERT(d->timer_irq); |
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|
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debug("[ dec5800: write to csr: 0x%08x ]\n", |
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(int)idata); |
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} |
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break; |
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default: |
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if (writeflag==MEM_READ) { |
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debug("[ dec5800: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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} else { |
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debug("[ dec5800: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, (int)idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(dec5800) |
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{ |
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struct dec5800_data *d; |
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char tmpstr[200]; |
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int i; |
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|
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d = malloc(sizeof(struct dec5800_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct dec5800_data)); |
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|
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snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path); |
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INTERRUPT_CONNECT(tmpstr, d->cpu_irq); |
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|
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snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path); |
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INTERRUPT_CONNECT(tmpstr, d->timer_irq); |
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|
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/* Register 32 CSR interrupts, corresponding to bits in the CSR: */ |
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for (i=0; i<32; i++) { |
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char n[200]; |
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struct interrupt template; |
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snprintf(n, sizeof(n), "%s.dec5800.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = i; |
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template.name = n; |
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template.extra = d; |
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template.interrupt_assert = dec5800_interrupt_assert; |
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template.interrupt_deassert = dec5800_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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|
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memory_device_register(devinit->machine->memory, "dec5800", |
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devinit->addr, DEV_DEC5800_LENGTH, dev_dec5800_access, |
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d, DM_DEFAULT, NULL); |
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memory_device_register(devinit->machine->memory, "dec5800_vectors", |
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devinit->addr + 0x30000000, 0x100, dev_dec5800_vectors_access, |
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d, DM_DEFAULT, NULL); |
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machine_add_tickfunction(devinit->machine, dev_dec5800_tick, |
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d, 14, 0.0); |
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|
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return 1; |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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#include "bireg.h" |
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|
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/* 16 slots, 0x2000 bytes each */ |
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#define DEV_DECBI_LENGTH 0x20000 |
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|
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struct decbi_data { |
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int csr[NNODEBI]; |
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}; |
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|
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|
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DEVICE_ACCESS(decbi) |
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{ |
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uint64_t idata = 0, odata = 0; |
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int node_nr; |
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struct decbi_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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relative_addr += BI_NODESIZE; /* HACK */ |
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|
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node_nr = relative_addr / BI_NODESIZE; |
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relative_addr &= (BI_NODESIZE - 1); |
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|
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/* TODO: This "1" here is the max node number in actual use. */ |
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if (node_nr > 1 || node_nr >= NNODEBI) |
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return 0; |
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|
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switch (relative_addr) { |
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case BIREG_DTYPE: |
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if (writeflag==MEM_READ) { |
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/* |
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* This is a list of the devices in our BI slots: |
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*/ |
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switch (node_nr) { |
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case 1: odata = BIDT_KDB50; break; /* Disk */ |
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/* case 2: odata = BIDT_DEBNA; break; */ |
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/* BIDT_DEBNA = Ethernet */ |
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/* case 3: odata = BIDT_MS820; break; */ |
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/* BIDT_MS820 = Memory */ |
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default: |
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/* No device. */ |
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odata = 0; |
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} |
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|
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debug("[ decbi: (node %i) read from BIREG_DTYPE:" |
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" 0x%x ]\n", node_nr, (int)odata); |
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} else { |
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debug("[ decbi: (node %i) attempt to write to " |
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"BIREG_DTYPE: 0x%08x ]\n", node_nr, (int)idata); |
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} |
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break; |
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case BIREG_VAXBICSR: |
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if (writeflag==MEM_READ) { |
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odata = (d->csr[node_nr] & ~BICSR_NODEMASK) | node_nr; |
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debug("[ decbi: (node %i) read from BIREG_" |
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"VAXBICSR: 0x%x ]\n", node_nr, (int)odata); |
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} else { |
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d->csr[node_nr] = idata; |
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debug("[ decbi: (node %i) attempt to write to " |
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"BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (int)idata); |
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} |
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break; |
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case 0xf4: |
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if (writeflag==MEM_READ) { |
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odata = 0xffff; /* ? */ |
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debug("[ decbi: (node %i) read from 0xf4: " |
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"0x%x ]\n", node_nr, (int)odata); |
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} else { |
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debug("[ decbi: (node %i) attempt to write " |
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"to 0xf4: 0x%08x ]\n", node_nr, (int)idata); |
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} |
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break; |
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default: |
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if (writeflag==MEM_READ) { |
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debug("[ decbi: (node %i) read from unimplemented " |
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"0x%08lx ]\n", node_nr, (long)relative_addr, |
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(int)odata); |
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} else { |
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debug("[ decbi: (node %i) write to unimplemented " |
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"0x%08lx: 0x%08x ]\n", node_nr, |
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(long)relative_addr, (int)idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(decbi) |
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{ |
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struct decbi_data *d; |
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|
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d = malloc(sizeof(struct decbi_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct decbi_data)); |
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|
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memory_device_register(devinit->machine->memory, "decbi", |
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devinit->addr + 0x2000, DEV_DECBI_LENGTH - 0x2000, |
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dev_decbi_access, d, DM_DEFAULT, NULL); |
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|
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return 1; |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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/* |
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* CCA, "Console Communication Area" for a DEC 5800 SMP system. |
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*/ |
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|
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struct deccca_data { |
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int dummy; |
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}; |
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|
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|
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DEVICE_ACCESS(deccca) |
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{ |
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uint64_t idata = 0, odata = 0; |
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/* struct deccca_data *d = extra; */ |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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switch (relative_addr) { |
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case 6: |
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case 7: |
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/* CCA "ID" bytes? These must be here, or Ultrix complains. */ |
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if (writeflag == MEM_READ) |
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odata = 67; |
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break; |
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case 8: |
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if (writeflag == MEM_READ) |
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odata = cpu->machine->ncpus; |
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break; |
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case 20: |
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if (writeflag == MEM_READ) |
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odata = (1 << cpu->machine->ncpus) - 1; |
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/* one bit for each cpu */ |
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break; |
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case 28: |
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if (writeflag == MEM_READ) |
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odata = (1 << cpu->machine->ncpus) - 1; |
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/* one bit for each enabled(?) cpu */ |
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break; |
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default: |
378 |
if (writeflag==MEM_READ) { |
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debug("[ deccca: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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} else { |
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debug("[ deccca: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, (int)idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
392 |
|
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|
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/* |
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* dev_deccca_init(): |
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*/ |
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void dev_deccca_init(struct memory *mem, uint64_t baseaddr) |
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{ |
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struct deccca_data *d; |
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|
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d = malloc(sizeof(struct deccca_data)); |
402 |
if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct deccca_data)); |
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|
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memory_device_register(mem, "deccca", baseaddr, DEV_DECCCA_LENGTH, |
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dev_deccca_access, d, DM_DEFAULT, NULL); |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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/* |
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* DEC 5800 XMI (this has to do with SMP...) |
418 |
*/ |
419 |
|
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#include "xmireg.h" |
421 |
|
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struct decxmi_data { |
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uint32_t reg_0xc[NNODEXMI]; |
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}; |
425 |
|
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|
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/* |
428 |
* dev_decxmi_access(): |
429 |
*/ |
430 |
DEVICE_ACCESS(decxmi) |
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{ |
432 |
uint64_t idata = 0, odata = 0; |
433 |
int node_nr; |
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struct decxmi_data *d = extra; |
435 |
|
436 |
if (writeflag == MEM_WRITE) |
437 |
idata = memory_readmax64(cpu, data, len); |
438 |
|
439 |
node_nr = relative_addr / XMI_NODESIZE; |
440 |
relative_addr &= (XMI_NODESIZE - 1); |
441 |
|
442 |
if (node_nr >= cpu->machine->ncpus + 1 || node_nr >= NNODEXMI) |
443 |
return 0; |
444 |
|
445 |
switch (relative_addr) { |
446 |
case XMI_TYPE: |
447 |
if (writeflag == MEM_READ) { |
448 |
/* |
449 |
* The first node is an XMI->BI adapter node, and then |
450 |
* there are n CPU nodes. |
451 |
*/ |
452 |
odata = XMIDT_ISIS; |
453 |
if (node_nr == 0) |
454 |
odata = XMIDT_DWMBA; |
455 |
|
456 |
debug("[ decxmi: (node %i) read from XMI_TYPE: " |
457 |
"0x%08x ]\n", node_nr, (int)odata); |
458 |
} else |
459 |
debug("[ decxmi: (node %i) write to XMI_TYPE: " |
460 |
"0x%08x ]\n", node_nr, (int)idata); |
461 |
break; |
462 |
case XMI_BUSERR: |
463 |
if (writeflag == MEM_READ) { |
464 |
odata = 0; |
465 |
debug("[ decxmi: (node %i) read from XMI_BUSERR: " |
466 |
"0x%08x ]\n", node_nr, (int)odata); |
467 |
} else |
468 |
debug("[ decxmi: (node %i) write to XMI_BUSERR: " |
469 |
"0x%08x ]\n", node_nr, (int)idata); |
470 |
break; |
471 |
case XMI_FAIL: |
472 |
if (writeflag == MEM_READ) { |
473 |
odata = 0; |
474 |
debug("[ decxmi: (node %i) read from XMI_FAIL: " |
475 |
"0x%08x ]\n", node_nr, (int)odata); |
476 |
} else |
477 |
debug("[ decxmi: (node %i) write to XMI_FAIL: " |
478 |
"0x%08x ]\n", node_nr, (int)idata); |
479 |
break; |
480 |
case 0xc: |
481 |
if (writeflag == MEM_READ) { |
482 |
odata = d->reg_0xc[node_nr]; |
483 |
debug("[ decxmi: (node %i) read from REG 0xC: " |
484 |
"0x%08x ]\n", node_nr, (int)odata); |
485 |
} else { |
486 |
d->reg_0xc[node_nr] = idata; |
487 |
debug("[ decxmi: (node %i) write to REG 0xC: " |
488 |
"0x%08x ]\n", node_nr, (int)idata); |
489 |
} |
490 |
break; |
491 |
default: |
492 |
if (writeflag==MEM_READ) { |
493 |
debug("[ decxmi: (node %i) read from unimplemented " |
494 |
"0x%08lx ]\n", node_nr, (long)relative_addr, |
495 |
(int)odata); |
496 |
} else { |
497 |
debug("[ decxmi: (node %i) write to unimplemented " |
498 |
"0x%08lx: 0x%08x ]\n", node_nr, |
499 |
(long)relative_addr, (int)idata); |
500 |
} |
501 |
} |
502 |
|
503 |
if (writeflag == MEM_READ) |
504 |
memory_writemax64(cpu, data, len, odata); |
505 |
|
506 |
return 1; |
507 |
} |
508 |
|
509 |
|
510 |
/* |
511 |
* dev_decxmi_init(): |
512 |
*/ |
513 |
void dev_decxmi_init(struct memory *mem, uint64_t baseaddr) |
514 |
{ |
515 |
struct decxmi_data *d; |
516 |
|
517 |
d = malloc(sizeof(struct decxmi_data)); |
518 |
if (d == NULL) { |
519 |
fprintf(stderr, "out of memory\n"); |
520 |
exit(1); |
521 |
} |
522 |
memset(d, 0, sizeof(struct decxmi_data)); |
523 |
|
524 |
memory_device_register(mem, "decxmi", baseaddr, DEV_DECXMI_LENGTH, |
525 |
dev_decxmi_access, d, DM_DEFAULT, NULL); |
526 |
} |
527 |
|