/[gxemul]/trunk/src/devices/dev_dec21143.c
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Contents of /trunk/src/devices/dev_dec21143.c

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 28369 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_dec21143.c,v 1.26 2006/08/21 14:44:22 debug Exp $
29 *
30 * DEC 21143 ("Tulip") ethernet controller. Implemented from Intel document
31 * 278074-001 ("21143 PC/CardBus 10/100Mb/s Ethernet LAN Controller") and by
32 * reverse-engineering OpenBSD and NetBSD sources.
33 *
34 * This device emulates several sub-components:
35 *
36 * 21143: This is the actual ethernet controller.
37 *
38 * MII: The "physical" network interface.
39 *
40 * SROM: A ROM area containing setting such as which MAC address to
41 * use, and info about the MII.
42 *
43 *
44 * TODO:
45 * o) Handle _writes_ to MII registers.
46 * o) Make it work with modern Linux kernels (as a guest OS).
47 * o) Endianness for descriptors? If necessary.
48 * o) Actually handle the "Setup" packet.
49 * o) MAC filtering on incoming packets.
50 * o) Don't hardcode as many values.
51 */
52
53 #include <stdio.h>
54 #include <stdlib.h>
55 #include <string.h>
56
57 #include "cpu.h"
58 #include "device.h"
59 #include "devices.h"
60 #include "emul.h"
61 #include "machine.h"
62 #include "memory.h"
63 #include "misc.h"
64 #include "net.h"
65
66 #include "mii.h"
67 #include "tulipreg.h"
68
69
70 /* #define debug fatal */
71
72 #define DEC21143_TICK_SHIFT 16
73
74 #define N_REGS 32
75 #define ROM_WIDTH 6
76
77 struct dec21143_data {
78 int irq_nr;
79 int irq_asserted;
80
81 /* PCI: */
82 int pci_little_endian;
83
84 /* Ethernet address, and a network which we are connected to: */
85 uint8_t mac[6];
86 struct net *net;
87
88 /* SROM emulation: */
89 uint8_t srom[1 << (ROM_WIDTH + 1)];
90 int srom_curbit;
91 int srom_opcode;
92 int srom_opcode_has_started;
93 int srom_addr;
94
95 /* MII PHY emulation: */
96 uint16_t mii_phy_reg[MII_NPHY * 32];
97 int mii_state;
98 int mii_bit;
99 int mii_opcode;
100 int mii_phyaddr;
101 int mii_regaddr;
102
103 /* 21143 registers: */
104 uint32_t reg[N_REGS];
105
106 /* Internal TX state: */
107 uint64_t cur_tx_addr;
108 unsigned char *cur_tx_buf;
109 int cur_tx_buf_len;
110 int tx_idling;
111 int tx_idling_threshold;
112
113 /* Internal RX state: */
114 uint64_t cur_rx_addr;
115 unsigned char *cur_rx_buf;
116 int cur_rx_buf_len;
117 int cur_rx_offset;
118 };
119
120
121 /* Internal states during MII data stream decode: */
122 #define MII_STATE_RESET 0
123 #define MII_STATE_START_WAIT 1
124 #define MII_STATE_READ_OP 2
125 #define MII_STATE_READ_PHYADDR_REGADDR 3
126 #define MII_STATE_A 4
127 #define MII_STATE_D 5
128 #define MII_STATE_IDLE 6
129
130
131 /*
132 * dec21143_rx():
133 *
134 * Receive a packet. (If there is no current packet, then check for newly
135 * arrived ones. If the current packet couldn't be fully transfered the
136 * last time, then continue on that packet.)
137 */
138 int dec21143_rx(struct cpu *cpu, struct dec21143_data *d)
139 {
140 uint64_t addr = d->cur_rx_addr, bufaddr;
141 unsigned char descr[16];
142 uint32_t rdes0, rdes1, rdes2, rdes3;
143 int bufsize, buf1_size, buf2_size, i, writeback_len = 4, to_xfer;
144
145 /* No current packet? Then check for new ones. */
146 if (d->cur_rx_buf == NULL) {
147 /* Nothing available? Then abort. */
148 if (!net_ethernet_rx_avail(d->net, d))
149 return 0;
150
151 /* Get the next packet into our buffer: */
152 net_ethernet_rx(d->net, d, &d->cur_rx_buf,
153 &d->cur_rx_buf_len);
154
155 /* Append a 4 byte CRC: */
156 d->cur_rx_buf_len += 4;
157 d->cur_rx_buf = realloc(d->cur_rx_buf, d->cur_rx_buf_len);
158 if (d->cur_rx_buf == NULL) {
159 fatal("dec21143_rx(): out of memory\n");
160 exit(1);
161 }
162 /* Well... the CRC is just zeros, for now. */
163 memset(d->cur_rx_buf + d->cur_rx_buf_len - 4, 0, 4);
164
165 d->cur_rx_offset = 0;
166 }
167
168 /* fatal("{ dec21143_rx: base = 0x%08x }\n", (int)addr); */
169 addr &= 0x7fffffff;
170
171 if (!cpu->memory_rw(cpu, cpu->mem, addr, descr, sizeof(uint32_t),
172 MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
173 fatal("[ dec21143_rx: memory_rw failed! ]\n");
174 return 0;
175 }
176
177 rdes0 = descr[0] + (descr[1]<<8) + (descr[2]<<16) + (descr[3]<<24);
178
179 /* Only use descriptors owned by the 21143: */
180 if (!(rdes0 & TDSTAT_OWN)) {
181 d->reg[CSR_STATUS/8] |= STATUS_RU;
182 return 0;
183 }
184
185 if (!cpu->memory_rw(cpu, cpu->mem, addr + sizeof(uint32_t), descr +
186 sizeof(uint32_t), sizeof(uint32_t) * 3, MEM_READ, PHYSICAL |
187 NO_EXCEPTIONS)) {
188 fatal("[ dec21143_rx: memory_rw failed! ]\n");
189 return 0;
190 }
191
192 rdes1 = descr[4] + (descr[5]<<8) + (descr[6]<<16) + (descr[7]<<24);
193 rdes2 = descr[8] + (descr[9]<<8) + (descr[10]<<16) + (descr[11]<<24);
194 rdes3 = descr[12] + (descr[13]<<8) + (descr[14]<<16) + (descr[15]<<24);
195
196 buf1_size = rdes1 & TDCTL_SIZE1;
197 buf2_size = (rdes1 & TDCTL_SIZE2) >> TDCTL_SIZE2_SHIFT;
198 bufaddr = buf1_size? rdes2 : rdes3;
199 bufsize = buf1_size? buf1_size : buf2_size;
200
201 d->reg[CSR_STATUS/8] &= ~STATUS_RS;
202
203 if (rdes1 & TDCTL_ER)
204 d->cur_rx_addr = d->reg[CSR_RXLIST / 8];
205 else {
206 if (rdes1 & TDCTL_CH)
207 d->cur_rx_addr = rdes3;
208 else
209 d->cur_rx_addr += 4 * sizeof(uint32_t);
210 }
211
212 debug("{ RX (%llx): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
213 (long long)addr, rdes0, rdes1, rdes2, rdes3, bufsize, (int)bufaddr);
214 bufaddr &= 0x7fffffff;
215
216 /* Turn off all status bits, and give up ownership: */
217 rdes0 = 0x00000000;
218
219 to_xfer = d->cur_rx_buf_len - d->cur_rx_offset;
220 if (to_xfer > bufsize)
221 to_xfer = bufsize;
222
223 /* DMA bytes from the packet into emulated physical memory: */
224 for (i=0; i<to_xfer; i++) {
225 cpu->memory_rw(cpu, cpu->mem, bufaddr + i,
226 d->cur_rx_buf + d->cur_rx_offset + i, 1, MEM_WRITE,
227 PHYSICAL | NO_EXCEPTIONS);
228 /* fatal(" %02x", d->cur_rx_buf[d->cur_rx_offset + i]); */
229 }
230
231 /* Was this the first buffer in a frame? Then mark it as such. */
232 if (d->cur_rx_offset == 0)
233 rdes0 |= TDSTAT_Rx_FS;
234
235 d->cur_rx_offset += to_xfer;
236
237 /* Frame completed? */
238 if (d->cur_rx_offset >= d->cur_rx_buf_len) {
239 rdes0 |= TDSTAT_Rx_LS;
240
241 /* Set the frame length: */
242 rdes0 |= (d->cur_rx_buf_len << 16) & TDSTAT_Rx_FL;
243
244 /* Frame too long? (1518 is max ethernet frame length) */
245 if (d->cur_rx_buf_len > 1518)
246 rdes0 |= TDSTAT_Rx_TL;
247
248 /* Cause a receiver interrupt: */
249 d->reg[CSR_STATUS/8] |= STATUS_RI;
250
251 free(d->cur_rx_buf);
252 d->cur_rx_buf = NULL;
253 d->cur_rx_buf_len = 0;
254 }
255
256 /* Descriptor writeback: */
257 descr[ 0] = rdes0; descr[ 1] = rdes0 >> 8;
258 descr[ 2] = rdes0 >> 16; descr[ 3] = rdes0 >> 24;
259 if (writeback_len > 1) {
260 descr[ 4] = rdes1; descr[ 5] = rdes1 >> 8;
261 descr[ 6] = rdes1 >> 16; descr[ 7] = rdes1 >> 24;
262 descr[ 8] = rdes2; descr[ 9] = rdes2 >> 8;
263 descr[10] = rdes2 >> 16; descr[11] = rdes2 >> 24;
264 descr[12] = rdes3; descr[13] = rdes3 >> 8;
265 descr[14] = rdes3 >> 16; descr[15] = rdes3 >> 24;
266 }
267
268 if (!cpu->memory_rw(cpu, cpu->mem, addr, descr, sizeof(uint32_t)
269 * writeback_len, MEM_WRITE, PHYSICAL | NO_EXCEPTIONS)) {
270 fatal("[ dec21143_rx: memory_rw failed! ]\n");
271 return 0;
272 }
273
274 return 1;
275 }
276
277
278 /*
279 * dec21143_tx():
280 *
281 * Transmit a packet, if the guest OS has marked a descriptor as containing
282 * data to transmit.
283 */
284 int dec21143_tx(struct cpu *cpu, struct dec21143_data *d)
285 {
286 uint64_t addr = d->cur_tx_addr, bufaddr;
287 unsigned char descr[16];
288 uint32_t tdes0, tdes1, tdes2, tdes3;
289 int bufsize, buf1_size, buf2_size, i, writeback_len = 4;
290
291 addr &= 0x7fffffff;
292
293 if (!cpu->memory_rw(cpu, cpu->mem, addr, descr, sizeof(uint32_t),
294 MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
295 fatal("[ dec21143_tx: memory_rw failed! ]\n");
296 return 0;
297 }
298
299 tdes0 = descr[0] + (descr[1]<<8) + (descr[2]<<16) + (descr[3]<<24);
300
301 /* fatal("{ dec21143_tx: base=0x%08x, tdes0=0x%08x }\n",
302 (int)addr, (int)tdes0); */
303
304 /* Only process packets owned by the 21143: */
305 if (!(tdes0 & TDSTAT_OWN)) {
306 if (d->tx_idling > d->tx_idling_threshold) {
307 d->reg[CSR_STATUS/8] |= STATUS_TU;
308 d->tx_idling = 0;
309 } else
310 d->tx_idling ++;
311 return 0;
312 }
313
314 if (!cpu->memory_rw(cpu, cpu->mem, addr + sizeof(uint32_t), descr +
315 sizeof(uint32_t), sizeof(uint32_t) * 3, MEM_READ, PHYSICAL |
316 NO_EXCEPTIONS)) {
317 fatal("[ dec21143_tx: memory_rw failed! ]\n");
318 return 0;
319 }
320
321 tdes1 = descr[4] + (descr[5]<<8) + (descr[6]<<16) + (descr[7]<<24);
322 tdes2 = descr[8] + (descr[9]<<8) + (descr[10]<<16) + (descr[11]<<24);
323 tdes3 = descr[12] + (descr[13]<<8) + (descr[14]<<16) + (descr[15]<<24);
324
325 buf1_size = tdes1 & TDCTL_SIZE1;
326 buf2_size = (tdes1 & TDCTL_SIZE2) >> TDCTL_SIZE2_SHIFT;
327 bufaddr = buf1_size? tdes2 : tdes3;
328 bufsize = buf1_size? buf1_size : buf2_size;
329
330 d->reg[CSR_STATUS/8] &= ~STATUS_TS;
331
332 if (tdes1 & TDCTL_ER)
333 d->cur_tx_addr = d->reg[CSR_TXLIST / 8];
334 else {
335 if (tdes1 & TDCTL_CH)
336 d->cur_tx_addr = tdes3;
337 else
338 d->cur_tx_addr += 4 * sizeof(uint32_t);
339 }
340
341 /*
342 fatal("{ TX (%llx): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
343 (long long)addr, tdes0, tdes1, tdes2, tdes3, bufsize, (int)bufaddr);
344 */
345 bufaddr &= 0x7fffffff;
346
347 /* Assume no error: */
348 tdes0 &= ~ (TDSTAT_Tx_UF | TDSTAT_Tx_EC | TDSTAT_Tx_LC
349 | TDSTAT_Tx_NC | TDSTAT_Tx_LO | TDSTAT_Tx_TO | TDSTAT_ES);
350
351 if (tdes1 & TDCTL_Tx_SET) {
352 /*
353 * Setup Packet.
354 *
355 * TODO. For now, just ignore it, and pretend it worked.
356 */
357 /* fatal("{ TX: setup packet }\n"); */
358 if (bufsize != 192)
359 fatal("[ dec21143: setup packet len = %i, should be"
360 " 192! ]\n", (int)bufsize);
361 if (tdes1 & TDCTL_Tx_IC)
362 d->reg[CSR_STATUS/8] |= STATUS_TI;
363 /* New descriptor values, according to the docs: */
364 tdes0 = 0x7fffffff; tdes1 = 0xffffffff;
365 tdes2 = 0xffffffff; tdes3 = 0xffffffff;
366 } else {
367 /*
368 * Data Packet.
369 */
370 /* fatal("{ TX: data packet: "); */
371 if (tdes1 & TDCTL_Tx_FS) {
372 /* First segment. Let's allocate a new buffer: */
373 /* fatal("new frame }\n"); */
374 d->cur_tx_buf = malloc(bufsize);
375 d->cur_tx_buf_len = 0;
376 } else {
377 /* Not first segment. Increase the length of
378 the current buffer: */
379 /* fatal("continuing last frame }\n"); */
380 d->cur_tx_buf = realloc(d->cur_tx_buf,
381 d->cur_tx_buf_len + bufsize);
382 }
383
384 if (d->cur_tx_buf == NULL) {
385 fatal("dec21143_tx(): out of memory\n");
386 exit(1);
387 }
388
389 /* "DMA" data from emulated physical memory into the buf: */
390 for (i=0; i<bufsize; i++) {
391 cpu->memory_rw(cpu, cpu->mem, bufaddr + i,
392 d->cur_tx_buf + d->cur_tx_buf_len + i, 1, MEM_READ,
393 PHYSICAL | NO_EXCEPTIONS);
394 /* fatal(" %02x", d->cur_tx_buf[
395 d->cur_tx_buf_len + i]); */
396 }
397
398 d->cur_tx_buf_len += bufsize;
399
400 /* Last segment? Then actually transmit it: */
401 if (tdes1 & TDCTL_Tx_LS) {
402 /* fatal("{ TX: data frame complete. }\n"); */
403 if (d->net != NULL) {
404 net_ethernet_tx(d->net, d, d->cur_tx_buf,
405 d->cur_tx_buf_len);
406 } else {
407 static int warn = 0;
408 if (!warn)
409 fatal("[ dec21143: WARNING! Not "
410 "connected to a network! ]\n");
411 warn = 1;
412 }
413
414 free(d->cur_tx_buf);
415 d->cur_tx_buf = NULL;
416 d->cur_tx_buf_len = 0;
417
418 /* TODO: Shouldn't the OWN bit be cleared on all
419 kinds of segments, not just the Last? */
420
421 /* We are done. */
422 tdes0 &= ~TDSTAT_OWN;
423 writeback_len = 1;
424
425 /* Interrupt, if Tx_IC is set: */
426 if (tdes1 & TDCTL_Tx_IC)
427 d->reg[CSR_STATUS/8] |= STATUS_TI;
428 }
429 }
430
431 /* Error summary: */
432 if (tdes0 & (TDSTAT_Tx_UF | TDSTAT_Tx_EC | TDSTAT_Tx_LC
433 | TDSTAT_Tx_NC | TDSTAT_Tx_LO | TDSTAT_Tx_TO))
434 tdes0 |= TDSTAT_ES;
435
436 /* Descriptor writeback: */
437 descr[ 0] = tdes0; descr[ 1] = tdes0 >> 8;
438 descr[ 2] = tdes0 >> 16; descr[ 3] = tdes0 >> 24;
439 if (writeback_len > 1) {
440 descr[ 4] = tdes1; descr[ 5] = tdes1 >> 8;
441 descr[ 6] = tdes1 >> 16; descr[ 7] = tdes1 >> 24;
442 descr[ 8] = tdes2; descr[ 9] = tdes2 >> 8;
443 descr[10] = tdes2 >> 16; descr[11] = tdes2 >> 24;
444 descr[12] = tdes3; descr[13] = tdes3 >> 8;
445 descr[14] = tdes3 >> 16; descr[15] = tdes3 >> 24;
446 }
447
448 if (!cpu->memory_rw(cpu, cpu->mem, addr, descr, sizeof(uint32_t)
449 * writeback_len, MEM_WRITE, PHYSICAL | NO_EXCEPTIONS)) {
450 fatal("[ dec21143_tx: memory_rw failed! ]\n");
451 return 0;
452 }
453
454 return 1;
455 }
456
457
458 /*
459 * dev_dec21143_tick():
460 */
461 void dev_dec21143_tick(struct cpu *cpu, void *extra)
462 {
463 struct dec21143_data *d = extra;
464 int asserted;
465
466 if (d->reg[CSR_OPMODE / 8] & OPMODE_ST)
467 while (dec21143_tx(cpu, d))
468 ;
469
470 if (d->reg[CSR_OPMODE / 8] & OPMODE_SR)
471 while (dec21143_rx(cpu, d))
472 ;
473
474 /* Normal and Abnormal interrupt summary: */
475 d->reg[CSR_STATUS / 8] &= ~(STATUS_NIS | STATUS_AIS);
476 if (d->reg[CSR_STATUS / 8] & 0x00004845)
477 d->reg[CSR_STATUS / 8] |= STATUS_NIS;
478 if (d->reg[CSR_STATUS / 8] & 0x0c0037ba)
479 d->reg[CSR_STATUS / 8] |= STATUS_AIS;
480
481 asserted = d->reg[CSR_STATUS / 8] & d->reg[CSR_INTEN / 8] & 0x0c01ffff;
482 if (asserted) {
483 cpu_interrupt(cpu, d->irq_nr);
484 } else {
485 if (d->irq_asserted)
486 cpu_interrupt_ack(cpu, d->irq_nr);
487 }
488
489 /* Remember assertion flag: */
490 d->irq_asserted = asserted;
491 }
492
493
494 /*
495 * mii_access():
496 *
497 * This function handles accesses to the MII. Data streams seem to be of the
498 * following format:
499 *
500 * vv---- starting delimiter
501 * ... 01 xx yyyyy zzzzz a[a] dddddddddddddddd
502 * ^---- I am starting with mii_bit = 0 here
503 *
504 * where x = opcode (10 = read, 01 = write)
505 * y = PHY address
506 * z = register address
507 * a = on Reads: ACK bit (returned, should be 0)
508 * on Writes: _TWO_ dummy bits (10)
509 * d = 16 bits of data (MSB first)
510 */
511 static void mii_access(struct cpu *cpu, struct dec21143_data *d,
512 uint32_t oldreg, uint32_t idata)
513 {
514 int obit, ibit = 0;
515 uint16_t tmp;
516
517 /* Only care about data during clock cycles: */
518 if (!(idata & MIIROM_MDC))
519 return;
520
521 if (idata & MIIROM_MDC && oldreg & MIIROM_MDC)
522 return;
523
524 /* fatal("[ mii_access(): 0x%08x ]\n", (int)idata); */
525
526 if (idata & MIIROM_BR) {
527 fatal("[ mii_access(): MIIROM_BR: TODO ]\n");
528 return;
529 }
530
531 obit = idata & MIIROM_MDO? 1 : 0;
532
533 if (d->mii_state >= MII_STATE_START_WAIT &&
534 d->mii_state <= MII_STATE_READ_PHYADDR_REGADDR &&
535 idata & MIIROM_MIIDIR)
536 fatal("[ mii_access(): bad dir? ]\n");
537
538 switch (d->mii_state) {
539
540 case MII_STATE_RESET:
541 /* Wait for a starting delimiter (0 followed by 1). */
542 if (obit)
543 return;
544 if (idata & MIIROM_MIIDIR)
545 return;
546 /* fatal("[ mii_access(): got a 0 delimiter ]\n"); */
547 d->mii_state = MII_STATE_START_WAIT;
548 d->mii_opcode = 0;
549 d->mii_phyaddr = 0;
550 d->mii_regaddr = 0;
551 break;
552
553 case MII_STATE_START_WAIT:
554 /* Wait for a starting delimiter (0 followed by 1). */
555 if (!obit)
556 return;
557 if (idata & MIIROM_MIIDIR) {
558 d->mii_state = MII_STATE_RESET;
559 return;
560 }
561 /* fatal("[ mii_access(): got a 1 delimiter ]\n"); */
562 d->mii_state = MII_STATE_READ_OP;
563 d->mii_bit = 0;
564 break;
565
566 case MII_STATE_READ_OP:
567 if (d->mii_bit == 0) {
568 d->mii_opcode = obit << 1;
569 /* fatal("[ mii_access(): got first opcode bit "
570 "(%i) ]\n", obit); */
571 } else {
572 d->mii_opcode |= obit;
573 /* fatal("[ mii_access(): got opcode = %i ]\n",
574 d->mii_opcode); */
575 d->mii_state = MII_STATE_READ_PHYADDR_REGADDR;
576 }
577 d->mii_bit ++;
578 break;
579
580 case MII_STATE_READ_PHYADDR_REGADDR:
581 /* fatal("[ mii_access(): got phy/reg addr bit nr %i (%i)"
582 " ]\n", d->mii_bit - 2, obit); */
583 if (d->mii_bit <= 6)
584 d->mii_phyaddr |= obit << (6-d->mii_bit);
585 else
586 d->mii_regaddr |= obit << (11-d->mii_bit);
587 d->mii_bit ++;
588 if (d->mii_bit >= 12) {
589 /* fatal("[ mii_access(): phyaddr=0x%x regaddr=0x"
590 "%x ]\n", d->mii_phyaddr, d->mii_regaddr); */
591 d->mii_state = MII_STATE_A;
592 }
593 break;
594
595 case MII_STATE_A:
596 switch (d->mii_opcode) {
597 case MII_COMMAND_WRITE:
598 if (d->mii_bit >= 13)
599 d->mii_state = MII_STATE_D;
600 break;
601 case MII_COMMAND_READ:
602 ibit = 0;
603 d->mii_state = MII_STATE_D;
604 break;
605 default:debug("[ mii_access(): UNIMPLEMENTED MII opcode "
606 "%i (probably just a bug in GXemul's "
607 "MII data stream handling) ]\n", d->mii_opcode);
608 d->mii_state = MII_STATE_RESET;
609 }
610 d->mii_bit ++;
611 break;
612
613 case MII_STATE_D:
614 switch (d->mii_opcode) {
615 case MII_COMMAND_WRITE:
616 if (idata & MIIROM_MIIDIR)
617 fatal("[ mii_access(): write: bad dir? ]\n");
618 obit = obit? (0x8000 >> (d->mii_bit - 14)) : 0;
619 tmp = d->mii_phy_reg[(d->mii_phyaddr << 5) +
620 d->mii_regaddr] | obit;
621 if (d->mii_bit >= 29) {
622 d->mii_state = MII_STATE_IDLE;
623 debug("[ mii_access(): WRITE to phyaddr=0x%x "
624 "regaddr=0x%x: 0x%04x ]\n", d->mii_phyaddr,
625 d->mii_regaddr, tmp);
626 }
627 break;
628 case MII_COMMAND_READ:
629 if (!(idata & MIIROM_MIIDIR))
630 break;
631 tmp = d->mii_phy_reg[(d->mii_phyaddr << 5) +
632 d->mii_regaddr];
633 if (d->mii_bit == 13)
634 debug("[ mii_access(): READ phyaddr=0x%x "
635 "regaddr=0x%x: 0x%04x ]\n", d->mii_phyaddr,
636 d->mii_regaddr, tmp);
637 ibit = tmp & (0x8000 >> (d->mii_bit - 13));
638 if (d->mii_bit >= 28)
639 d->mii_state = MII_STATE_IDLE;
640 break;
641 }
642 d->mii_bit ++;
643 break;
644
645 case MII_STATE_IDLE:
646 d->mii_bit ++;
647 if (d->mii_bit >= 31)
648 d->mii_state = MII_STATE_RESET;
649 break;
650 }
651
652 d->reg[CSR_MIIROM / 8] &= ~MIIROM_MDI;
653 if (ibit)
654 d->reg[CSR_MIIROM / 8] |= MIIROM_MDI;
655 }
656
657
658 /*
659 * srom_access():
660 *
661 * This function handles reads from the Ethernet Address ROM. This is not a
662 * 100% correct implementation, as it was reverse-engineered from OpenBSD
663 * sources; it seems to work with OpenBSD, NetBSD, and Linux, though.
664 *
665 * Each transfer (if I understood this correctly) is of the following format:
666 *
667 * 1xx yyyyyy zzzzzzzzzzzzzzzz
668 *
669 * where 1xx = operation (6 means a Read),
670 * yyyyyy = ROM address
671 * zz...z = data
672 *
673 * y and z are _both_ read and written to at the same time; this enables the
674 * operating system to sense the number of bits in y (when reading, all y bits
675 * are 1 except the last one).
676 */
677 static void srom_access(struct cpu *cpu, struct dec21143_data *d,
678 uint32_t oldreg, uint32_t idata)
679 {
680 int obit, ibit;
681
682 /* debug("CSR9 WRITE! 0x%08x\n", (int)idata); */
683
684 /* New selection? Then reset internal state. */
685 if (idata & MIIROM_SR && !(oldreg & MIIROM_SR)) {
686 d->srom_curbit = 0;
687 d->srom_opcode = 0;
688 d->srom_opcode_has_started = 0;
689 d->srom_addr = 0;
690 }
691
692 /* Only care about data during clock cycles: */
693 if (!(idata & MIIROM_SROMSK))
694 return;
695
696 obit = 0;
697 ibit = idata & MIIROM_SROMDI? 1 : 0;
698 /* debug("CLOCK CYCLE! (bit %i): ", d->srom_curbit); */
699
700 /*
701 * Linux sends more zeroes before starting the actual opcode, than
702 * OpenBSD and NetBSD. Hopefully this is correct. (I'm just guessing
703 * that all opcodes should start with a 1, perhaps that's not really
704 * the case.)
705 */
706 if (!ibit && !d->srom_opcode_has_started)
707 return;
708
709 if (d->srom_curbit < 3) {
710 d->srom_opcode_has_started = 1;
711 d->srom_opcode <<= 1;
712 d->srom_opcode |= ibit;
713 /* debug("opcode input '%i'\n", ibit); */
714 } else {
715 switch (d->srom_opcode) {
716 case TULIP_SROM_OPC_READ:
717 if (d->srom_curbit < ROM_WIDTH + 3) {
718 obit = d->srom_curbit < ROM_WIDTH + 2;
719 d->srom_addr <<= 1;
720 d->srom_addr |= ibit;
721 } else {
722 uint16_t romword = d->srom[d->srom_addr*2]
723 + (d->srom[d->srom_addr*2+1] << 8);
724 if (d->srom_curbit == ROM_WIDTH + 3)
725 debug("[ dec21143: ROM read from offset"
726 " 0x%03x: 0x%04x ]\n",
727 d->srom_addr, romword);
728 obit = romword & (0x8000 >>
729 (d->srom_curbit - ROM_WIDTH - 3))? 1 : 0;
730 }
731 break;
732 default:fatal("[ dec21243: unimplemented SROM/EEPROM "
733 "opcode %i ]\n", d->srom_opcode);
734 }
735 d->reg[CSR_MIIROM / 8] &= ~MIIROM_SROMDO;
736 if (obit)
737 d->reg[CSR_MIIROM / 8] |= MIIROM_SROMDO;
738 /* debug("input '%i', output '%i'\n", ibit, obit); */
739 }
740
741 d->srom_curbit ++;
742
743 /*
744 * Done opcode + addr + data? Then restart. (At least NetBSD does
745 * sequential reads without turning selection off and then on.)
746 */
747 if (d->srom_curbit >= 3 + ROM_WIDTH + 16) {
748 d->srom_curbit = 0;
749 d->srom_opcode = 0;
750 d->srom_opcode_has_started = 0;
751 d->srom_addr = 0;
752 }
753 }
754
755
756 /*
757 * dec21143_reset():
758 *
759 * Set the 21143 registers, SROM, and MII data to reasonable values.
760 */
761 static void dec21143_reset(struct cpu *cpu, struct dec21143_data *d)
762 {
763 int leaf;
764
765 if (d->cur_rx_buf != NULL)
766 free(d->cur_rx_buf);
767 if (d->cur_tx_buf != NULL)
768 free(d->cur_tx_buf);
769 d->cur_rx_buf = d->cur_tx_buf = NULL;
770
771 memset(d->reg, 0, sizeof(uint32_t) * N_REGS);
772 memset(d->srom, 0, sizeof(d->srom));
773 memset(d->mii_phy_reg, 0, sizeof(d->mii_phy_reg));
774
775 /* Register values at reset, according to the manual: */
776 d->reg[CSR_BUSMODE / 8] = 0xfe000000; /* csr0 */
777 d->reg[CSR_MIIROM / 8] = 0xfff483ff; /* csr9 */
778 d->reg[CSR_SIACONN / 8] = 0xffff0000; /* csr13 */
779 d->reg[CSR_SIATXRX / 8] = 0xffffffff; /* csr14 */
780 d->reg[CSR_SIAGEN / 8] = 0x8ff00000; /* csr15 */
781
782 d->tx_idling_threshold = 10;
783 d->cur_rx_addr = d->cur_tx_addr = 0;
784
785 /* Version (= 1) and Chip count (= 1): */
786 d->srom[TULIP_ROM_SROM_FORMAT_VERION] = 1;
787 d->srom[TULIP_ROM_CHIP_COUNT] = 1;
788
789 /* Set the MAC address: */
790 memcpy(d->srom + TULIP_ROM_IEEE_NETWORK_ADDRESS, d->mac, 6);
791
792 leaf = 30;
793 d->srom[TULIP_ROM_CHIPn_DEVICE_NUMBER(0)] = 0;
794 d->srom[TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(0)] = leaf & 255;
795 d->srom[TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(0)+1] = leaf >> 8;
796
797 d->srom[leaf+TULIP_ROM_IL_SELECT_CONN_TYPE] = 0; /* Not used? */
798 d->srom[leaf+TULIP_ROM_IL_MEDIA_COUNT] = 2;
799 leaf += TULIP_ROM_IL_MEDIAn_BLOCK_BASE;
800
801 d->srom[leaf] = 7; /* descriptor length */
802 d->srom[leaf+1] = TULIP_ROM_MB_21142_SIA;
803 d->srom[leaf+2] = TULIP_ROM_MB_MEDIA_100TX;
804 /* here comes 4 bytes of GPIO control/data settings */
805 leaf += d->srom[leaf];
806
807 d->srom[leaf] = 15; /* descriptor length */
808 d->srom[leaf+1] = TULIP_ROM_MB_21142_MII;
809 d->srom[leaf+2] = 0; /* PHY nr */
810 d->srom[leaf+3] = 0; /* len of select sequence */
811 d->srom[leaf+4] = 0; /* len of reset sequence */
812 /* 5,6, 7,8, 9,10, 11,12, 13,14 = unused by GXemul */
813 leaf += d->srom[leaf];
814
815 /* MII PHY initial state: */
816 d->mii_state = MII_STATE_RESET;
817
818 /* PHY #0: */
819 d->mii_phy_reg[MII_BMSR] = BMSR_100TXFDX | BMSR_10TFDX |
820 BMSR_ACOMP | BMSR_ANEG | BMSR_LINK;
821 }
822
823
824 /*
825 * dev_dec21143_access():
826 */
827 DEVICE_ACCESS(dec21143)
828 {
829 struct dec21143_data *d = extra;
830 uint64_t idata = 0, odata = 0;
831 uint32_t oldreg = 0;
832 int regnr = relative_addr >> 3;
833
834 if (writeflag == MEM_WRITE)
835 idata = memory_readmax64(cpu, data, len | d->pci_little_endian);
836
837 if ((relative_addr & 7) == 0 && regnr < N_REGS) {
838 if (writeflag == MEM_READ) {
839 odata = d->reg[regnr];
840 } else {
841 oldreg = d->reg[regnr];
842 switch (regnr) {
843 case CSR_STATUS / 8: /* Zero-on-write */
844 d->reg[regnr] &= ~(idata & 0x0c01ffff);
845 break;
846 case CSR_MISSED / 8: /* Read only */
847 break;
848 default:d->reg[regnr] = idata;
849 }
850 }
851 } else
852 fatal("[ dec21143: WARNING! unaligned access (0x%x) ]\n",
853 (int)relative_addr);
854
855 switch (relative_addr) {
856
857 case CSR_BUSMODE: /* csr0 */
858 if (writeflag == MEM_WRITE) {
859 /* Software reset takes effect immediately. */
860 if (idata & BUSMODE_SWR) {
861 dec21143_reset(cpu, d);
862 idata &= ~BUSMODE_SWR;
863 }
864 }
865 break;
866
867 case CSR_TXPOLL: /* csr1 */
868 if (writeflag == MEM_READ)
869 fatal("[ dec21143: UNIMPLEMENTED READ from "
870 "txpoll ]\n");
871 d->tx_idling = d->tx_idling_threshold;
872 dev_dec21143_tick(cpu, extra);
873 break;
874
875 case CSR_RXPOLL: /* csr2 */
876 if (writeflag == MEM_READ)
877 fatal("[ dec21143: UNIMPLEMENTED READ from "
878 "rxpoll ]\n");
879 dev_dec21143_tick(cpu, extra);
880 break;
881
882 case CSR_RXLIST: /* csr3 */
883 if (writeflag == MEM_WRITE) {
884 debug("[ dec21143: setting RXLIST to 0x%x ]\n",
885 (int)idata);
886 if (idata & 0x3)
887 fatal("[ dec21143: WARNING! RXLIST not aligned"
888 "? (0x%llx) ]\n", (long long)idata);
889 idata &= ~0x3;
890 d->cur_rx_addr = idata;
891 }
892 break;
893
894 case CSR_TXLIST: /* csr4 */
895 if (writeflag == MEM_WRITE) {
896 debug("[ dec21143: setting TXLIST to 0x%x ]\n",
897 (int)idata);
898 if (idata & 0x3)
899 fatal("[ dec21143: WARNING! TXLIST not aligned"
900 "? (0x%llx) ]\n", (long long)idata);
901 idata &= ~0x3;
902 d->cur_tx_addr = idata;
903 }
904 break;
905
906 case CSR_STATUS: /* csr5 */
907 case CSR_INTEN: /* csr7 */
908 if (writeflag == MEM_WRITE) {
909 /* Recalculate interrupt assertion. */
910 dev_dec21143_tick(cpu, extra);
911 }
912 break;
913
914 case CSR_OPMODE: /* csr6: */
915 if (writeflag == MEM_WRITE) {
916 if (idata & 0x02000000) {
917 /* A must-be-one bit. */
918 idata &= ~0x02000000;
919 }
920 if (idata & OPMODE_ST) {
921 idata &= ~OPMODE_ST;
922 } else {
923 /* Turned off TX? Then idle: */
924 d->reg[CSR_STATUS/8] |= STATUS_TPS;
925 }
926 if (idata & OPMODE_SR) {
927 idata &= ~OPMODE_SR;
928 } else {
929 /* Turned off RX? Then go to stopped state: */
930 d->reg[CSR_STATUS/8] &= ~STATUS_RS;
931 }
932 idata &= ~(OPMODE_HBD | OPMODE_SCR | OPMODE_PCS
933 | OPMODE_PS | OPMODE_SF | OPMODE_TTM | OPMODE_FD);
934 if (idata & OPMODE_PNIC_IT) {
935 idata &= ~OPMODE_PNIC_IT;
936 d->tx_idling = d->tx_idling_threshold;
937 }
938 if (idata != 0) {
939 fatal("[ dec21143: UNIMPLEMENTED OPMODE bits"
940 ": 0x%08x ]\n", (int)idata);
941 }
942 dev_dec21143_tick(cpu, extra);
943 }
944 break;
945
946 case CSR_MISSED: /* csr8 */
947 break;
948
949 case CSR_MIIROM: /* csr9 */
950 if (writeflag == MEM_WRITE) {
951 if (idata & MIIROM_MDC)
952 mii_access(cpu, d, oldreg, idata);
953 else
954 srom_access(cpu, d, oldreg, idata);
955 }
956 break;
957
958 case CSR_SIASTAT: /* csr12 */
959 /* Auto-negotiation status = Good. */
960 odata = SIASTAT_ANS_FLPGOOD;
961 break;
962
963 case CSR_SIATXRX: /* csr14 */
964 /* Auto-negotiation Enabled */
965 odata = SIATXRX_ANE;
966 break;
967
968 case CSR_SIACONN: /* csr13 */
969 case CSR_SIAGEN: /* csr15 */
970 /* Don't print warnings for these, for now. */
971 break;
972
973 default:if (writeflag == MEM_READ)
974 fatal("[ dec21143: read from unimplemented 0x%02x ]\n",
975 (int)relative_addr);
976 else
977 fatal("[ dec21143: write to unimplemented 0x%02x: "
978 "0x%02x ]\n", (int)relative_addr, (int)idata);
979 }
980
981 if (writeflag == MEM_READ)
982 memory_writemax64(cpu, data, len | d->pci_little_endian, odata);
983
984 return 1;
985 }
986
987
988 DEVINIT(dec21143)
989 {
990 struct dec21143_data *d;
991 char name2[100];
992
993 d = malloc(sizeof(struct dec21143_data));
994 if (d == NULL) {
995 fprintf(stderr, "out of memory\n");
996 exit(1);
997 }
998 memset(d, 0, sizeof(struct dec21143_data));
999
1000 d->irq_nr = devinit->irq_nr;
1001 d->pci_little_endian = devinit->pci_little_endian;
1002
1003 net_generate_unique_mac(devinit->machine, d->mac);
1004 net_add_nic(devinit->machine->emul->net, d, d->mac);
1005 d->net = devinit->machine->emul->net;
1006
1007 dec21143_reset(devinit->machine->cpus[0], d);
1008
1009 snprintf(name2, sizeof(name2), "%s [%02x:%02x:%02x:%02x:%02x:%02x]",
1010 devinit->name, d->mac[0], d->mac[1], d->mac[2], d->mac[3],
1011 d->mac[4], d->mac[5]);
1012
1013 memory_device_register(devinit->machine->memory, name2,
1014 devinit->addr, 0x100, dev_dec21143_access, d, DM_DEFAULT, NULL);
1015
1016 machine_add_tickfunction(devinit->machine,
1017 dev_dec21143_tick, d, DEC21143_TICK_SHIFT, 0.0);
1018
1019 /*
1020 * NetBSD/cats uses memory accesses, OpenBSD/cats uses I/O registers.
1021 * Let's make a mirror from the memory range to the I/O range:
1022 */
1023 dev_ram_init(devinit->machine, devinit->addr2, 0x100, DEV_RAM_MIRROR
1024 | DEV_RAM_MIGHT_POINT_TO_DEVICES, devinit->addr);
1025
1026 return 1;
1027 }
1028

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