/[gxemul]/trunk/src/devices/dev_dc7085.c
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Contents of /trunk/src/devices/dev_dc7085.c

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (11 years, 11 months ago) by dpavlin
File MIME type: text/plain
File size: 8807 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 /*
2 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_dc7085.c,v 1.58 2006/09/06 04:55:35 debug Exp $
29 *
30 * DC7085 serial controller, used in some DECstation models.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "console.h"
38 #include "cpu.h"
39 #include "devices.h"
40 #include "machine.h"
41 #include "memory.h"
42 #include "misc.h"
43
44 #include "dc7085.h"
45
46
47 #define DC_TICK_SHIFT 14
48
49 #define MAX_QUEUE_LEN 32768
50
51 struct dc_data {
52 struct dc7085regs regs;
53
54 int console_handle;
55
56 /* For slow_serial_interrupts_hack_for_linux: */
57 int just_transmitted_something;
58
59 unsigned char rx_queue_char[MAX_QUEUE_LEN];
60 char rx_queue_lineno[MAX_QUEUE_LEN];
61 int cur_rx_queue_pos_write;
62 int cur_rx_queue_pos_read;
63
64 int tx_scanner;
65
66 int irqnr;
67 int use_fb;
68
69 struct lk201_data lk201;
70 };
71
72
73 /*
74 * Add a character to the receive queue.
75 */
76 void add_to_rx_queue(void *e, int ch, int line_no)
77 {
78 struct dc_data *d = (struct dc_data *) e;
79 int entries_in_use = d->cur_rx_queue_pos_write -
80 d->cur_rx_queue_pos_read;
81
82 while (entries_in_use < 0)
83 entries_in_use += MAX_QUEUE_LEN;
84
85 /* Ignore mouse updates, if they come too often: */
86 if (entries_in_use > MAX_QUEUE_LEN/2 && line_no == DCMOUSE_PORT)
87 return;
88
89 d->rx_queue_char[d->cur_rx_queue_pos_write] = ch;
90 d->rx_queue_lineno[d->cur_rx_queue_pos_write] = line_no;
91 d->cur_rx_queue_pos_write ++;
92 if (d->cur_rx_queue_pos_write == MAX_QUEUE_LEN)
93 d->cur_rx_queue_pos_write = 0;
94
95 if (d->cur_rx_queue_pos_write == d->cur_rx_queue_pos_read)
96 fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
97 }
98
99
100 DEVICE_TICK(dc7085)
101 {
102 /*
103 * If a key is available from the keyboard, add it to the rx queue.
104 * If other bits are set, an interrupt might need to be caused.
105 */
106 struct dc_data *d = extra;
107 int avail;
108
109 if (cpu->machine->slow_serial_interrupts_hack_for_linux) {
110 /*
111 * Special hack to prevent Linux from Oopsing. (This makes
112 * interrupts not come as fast as possible.)
113 */
114 if (d->just_transmitted_something) {
115 d->just_transmitted_something --;
116 return;
117 }
118 }
119
120 d->regs.dc_csr &= ~CSR_RDONE;
121
122 if ((d->regs.dc_csr & CSR_MSE) && !(d->regs.dc_csr & CSR_TRDY)) {
123 int scanner_start = d->tx_scanner;
124
125 /* Loop until we've checked all 4 channels, or some
126 channel was ready to transmit: */
127
128 do {
129 d->tx_scanner = (d->tx_scanner + 1) % 4;
130
131 if (d->regs.dc_tcr & (1 << d->tx_scanner)) {
132 d->regs.dc_csr |= CSR_TRDY;
133 if (d->regs.dc_csr & CSR_TIE)
134 cpu_interrupt(cpu, d->irqnr);
135
136 d->regs.dc_csr &= ~CSR_TX_LINE_NUM;
137 d->regs.dc_csr |= (d->tx_scanner << 8);
138 }
139 } while (!(d->regs.dc_csr & CSR_TRDY) &&
140 d->tx_scanner != scanner_start);
141
142 /* We have to return here. NetBSD can handle both
143 rx and tx interrupts simultaneously, but Ultrix
144 doesn't like that? */
145
146 if (d->regs.dc_csr & CSR_TRDY)
147 return;
148 }
149
150 lk201_tick(cpu->machine, &d->lk201);
151
152 avail = d->cur_rx_queue_pos_write != d->cur_rx_queue_pos_read;
153
154 if (avail && (d->regs.dc_csr & CSR_MSE))
155 d->regs.dc_csr |= CSR_RDONE;
156
157 if ((d->regs.dc_csr & CSR_RDONE) && (d->regs.dc_csr & CSR_RIE))
158 cpu_interrupt(cpu, d->irqnr);
159 }
160
161
162 DEVICE_ACCESS(dc7085)
163 {
164 uint64_t idata = 0, odata = 0;
165 size_t i;
166 struct dc_data *d = extra;
167
168 if (writeflag == MEM_WRITE)
169 idata = memory_readmax64(cpu, data, len);
170
171 /* Always clear: */
172 d->regs.dc_csr &= ~CSR_CLR;
173
174 switch (relative_addr) {
175 case 0x00: /* CSR: Control and Status */
176 if (writeflag == MEM_WRITE) {
177 debug("[ dc7085 write to CSR: 0x%04x ]\n", idata);
178 idata &= (CSR_TIE | CSR_RIE | CSR_MSE | CSR_CLR
179 | CSR_MAINT);
180 d->regs.dc_csr &= ~(CSR_TIE | CSR_RIE | CSR_MSE
181 | CSR_CLR | CSR_MAINT);
182 d->regs.dc_csr |= idata;
183 if (!(d->regs.dc_csr & CSR_MSE))
184 d->regs.dc_csr &= ~(CSR_TRDY | CSR_RDONE);
185 goto do_return;
186 } else {
187 /* read: */
188
189 /* fatal("[ dc7085 read from CSR: (csr = 0x%04x) ]\n",
190 d->regs.dc_csr); */
191 odata = d->regs.dc_csr;
192 }
193 break;
194 case 0x08: /* LPR: */
195 if (writeflag == MEM_WRITE) {
196 debug("[ dc7085 write to LPR: 0x%04x ]\n", idata);
197 d->regs.dc_rbuf_lpr = idata;
198 goto do_return;
199 } else {
200 /* read: */
201 int avail = d->cur_rx_queue_pos_write !=
202 d->cur_rx_queue_pos_read;
203 int ch = 0, lineno = 0;
204 /* debug("[ dc7085 read from RBUF: "); */
205 if (avail) {
206 ch = d->rx_queue_char[d->cur_rx_queue_pos_read];
207 lineno = d->rx_queue_lineno[
208 d->cur_rx_queue_pos_read];
209 d->cur_rx_queue_pos_read++;
210 if (d->cur_rx_queue_pos_read == MAX_QUEUE_LEN)
211 d->cur_rx_queue_pos_read = 0;
212 /* if (ch >= ' ' && ch < 127)
213 debug("'%c'", ch);
214 else
215 debug("0x%x", ch);
216 debug(" for lineno %i ", lineno); */
217 } /* else
218 debug("empty ");
219 debug("]\n"); */
220 odata = (avail? RBUF_DVAL:0) |
221 (lineno << RBUF_LINE_NUM_SHIFT) | ch;
222
223 d->regs.dc_csr &= ~CSR_RDONE;
224 cpu_interrupt_ack(cpu, d->irqnr);
225
226 d->just_transmitted_something = 4;
227 }
228 break;
229 case 0x10: /* TCR: */
230 if (writeflag == MEM_WRITE) {
231 /* fatal("[ dc7085 write to TCR: 0x%04x) ]\n",
232 (int)idata); */
233 d->regs.dc_tcr = idata;
234 d->regs.dc_csr &= ~CSR_TRDY;
235 cpu_interrupt_ack(cpu, d->irqnr);
236 goto do_return;
237 } else {
238 /* read: */
239 /* debug("[ dc7085 read from TCR: (tcr = 0x%04x) ]\n",
240 d->regs.dc_tcr); */
241 odata = d->regs.dc_tcr;
242 }
243 break;
244 case 0x18: /* Modem status (R), transmit data (W) */
245 if (writeflag == MEM_WRITE) {
246 int line_no = (d->regs.dc_csr >>
247 RBUF_LINE_NUM_SHIFT) & 0x3;
248 idata &= 0xff;
249
250 lk201_tx_data(&d->lk201, line_no, idata);
251
252 d->regs.dc_csr &= ~CSR_TRDY;
253 cpu_interrupt_ack(cpu, d->irqnr);
254
255 d->just_transmitted_something = 4;
256 } else {
257 /* read: */
258 d->regs.dc_msr_tdr |= MSR_DSR2 | MSR_CD2 |
259 MSR_DSR3 | MSR_CD3;
260 debug("[ dc7085 read from MSR: (msr_tdr = 0x%04x) ]\n",
261 d->regs.dc_msr_tdr);
262 odata = d->regs.dc_msr_tdr;
263 }
264 break;
265 default:
266 if (writeflag==MEM_READ) {
267 debug("[ dc7085 read from 0x%08lx ]\n",
268 (long)relative_addr);
269 } else {
270 debug("[ dc7085 write to 0x%08lx:",
271 (long)relative_addr);
272 for (i=0; i<len; i++)
273 debug(" %02x", data[i]);
274 debug(" ]\n");
275 }
276 }
277
278 if (writeflag == MEM_READ)
279 memory_writemax64(cpu, data, len, odata);
280
281 do_return:
282 dev_dc7085_tick(cpu, extra);
283
284 return 1;
285 }
286
287
288 /*
289 * dev_dc7085_init():
290 *
291 * Initialize a dc7085 serial controller device. use_fb should be non-zero
292 * if a framebuffer device is used. Channel 0 will then be treated as a
293 * DECstation keyboard, instead of a plain serial console.
294 */
295 int dev_dc7085_init(struct machine *machine, struct memory *mem,
296 uint64_t baseaddr, int irq_nr, int use_fb)
297 {
298 struct dc_data *d;
299
300 d = malloc(sizeof(struct dc_data));
301 if (d == NULL) {
302 fprintf(stderr, "out of memory\n");
303 exit(1);
304 }
305 memset(d, 0, sizeof(struct dc_data));
306 d->irqnr = irq_nr;
307 d->use_fb = use_fb;
308
309 d->regs.dc_csr = CSR_TRDY | CSR_MSE;
310 d->regs.dc_tcr = 0x00;
311
312 d->console_handle = console_start_slave(machine, "DC7085", 1);
313
314 lk201_init(&d->lk201, use_fb, add_to_rx_queue, d->console_handle, d);
315
316 memory_device_register(mem, "dc7085", baseaddr, DEV_DC7085_LENGTH,
317 dev_dc7085_access, d, DM_DEFAULT, NULL);
318 machine_add_tickfunction(machine, dev_dc7085_tick, d,
319 DC_TICK_SHIFT, 0.0);
320
321 return d->console_handle;
322 }
323

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