/[gxemul]/trunk/src/devices/dev_dc7085.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Diff of /trunk/src/devices/dev_dc7085.c

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revision 41 by dpavlin, Mon Oct 8 16:21:17 2007 UTC revision 42 by dpavlin, Mon Oct 8 16:22:32 2007 UTC
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_dc7085.c,v 1.60 2006/12/31 21:35:26 debug Exp $   *  $Id: dev_dc7085.c,v 1.62 2007/06/15 18:44:19 debug Exp $
29   *     *  
30   *  DC7085 serial controller, used in some DECstation models.   *  COMMENT: DC7085 serial controller, used in some DECstation models
31   */   */
32    
33  #include <stdio.h>  #include <stdio.h>
# Line 161  DEVICE_TICK(dc7085) Line 161  DEVICE_TICK(dc7085)
161    
162  DEVICE_ACCESS(dc7085)  DEVICE_ACCESS(dc7085)
163  {  {
164            struct dc_data *d = extra;
165          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
166          size_t i;          size_t i;
         struct dc_data *d = extra;  
167    
168          if (writeflag == MEM_WRITE)          if (writeflag == MEM_WRITE)
169                  idata = memory_readmax64(cpu, data, len);                  idata = memory_readmax64(cpu, data, len);
# Line 172  DEVICE_ACCESS(dc7085) Line 172  DEVICE_ACCESS(dc7085)
172          d->regs.dc_csr &= ~CSR_CLR;          d->regs.dc_csr &= ~CSR_CLR;
173    
174          switch (relative_addr) {          switch (relative_addr) {
175    
176          case 0x00:      /*  CSR:  Control and Status  */          case 0x00:      /*  CSR:  Control and Status  */
177                  if (writeflag == MEM_WRITE) {                  if (writeflag == MEM_WRITE) {
178                          debug("[ dc7085 write to CSR: 0x%04x ]\n", idata);                          debug("[ dc7085 write to CSR: 0x%04x ]\n", idata);
# Line 191  DEVICE_ACCESS(dc7085) Line 192  DEVICE_ACCESS(dc7085)
192                          odata = d->regs.dc_csr;                          odata = d->regs.dc_csr;
193                  }                  }
194                  break;                  break;
195    
196          case 0x08:      /*  LPR:  */          case 0x08:      /*  LPR:  */
197                  if (writeflag == MEM_WRITE) {                  if (writeflag == MEM_WRITE) {
198                          debug("[ dc7085 write to LPR: 0x%04x ]\n", idata);                          debug("[ dc7085 write to LPR: 0x%04x ]\n", idata);
# Line 226  DEVICE_ACCESS(dc7085) Line 228  DEVICE_ACCESS(dc7085)
228                          d->just_transmitted_something = 4;                          d->just_transmitted_something = 4;
229                  }                  }
230                  break;                  break;
231    
232          case 0x10:      /*  TCR:  */          case 0x10:      /*  TCR:  */
233                  if (writeflag == MEM_WRITE) {                  if (writeflag == MEM_WRITE) {
234                          /*  fatal("[ dc7085 write to TCR: 0x%04x) ]\n",                          /*  fatal("[ dc7085 write to TCR: 0x%04x) ]\n",
# Line 241  DEVICE_ACCESS(dc7085) Line 244  DEVICE_ACCESS(dc7085)
244                          odata = d->regs.dc_tcr;                          odata = d->regs.dc_tcr;
245                  }                  }
246                  break;                  break;
247    
248          case 0x18:      /*  Modem status (R), transmit data (W)  */          case 0x18:      /*  Modem status (R), transmit data (W)  */
249                  if (writeflag == MEM_WRITE) {                  if (writeflag == MEM_WRITE) {
250                          int line_no = (d->regs.dc_csr >>                          int line_no = (d->regs.dc_csr >>
# Line 262  DEVICE_ACCESS(dc7085) Line 266  DEVICE_ACCESS(dc7085)
266                          odata = d->regs.dc_msr_tdr;                          odata = d->regs.dc_msr_tdr;
267                  }                  }
268                  break;                  break;
269    
270          default:          default:
271                  if (writeflag==MEM_READ) {                  if (writeflag==MEM_READ) {
272                          debug("[ dc7085 read from 0x%08lx ]\n",                          debug("[ dc7085 read from 0x%08lx ]\n",
# Line 297  int dev_dc7085_init(struct machine *mach Line 302  int dev_dc7085_init(struct machine *mach
302  {  {
303          struct dc_data *d;          struct dc_data *d;
304    
305          d = malloc(sizeof(struct dc_data));          CHECK_ALLOCATION(d = malloc(sizeof(struct dc_data)));
         if (d == NULL) {  
                 fprintf(stderr, "out of memory\n");  
                 exit(1);  
         }  
306          memset(d, 0, sizeof(struct dc_data));          memset(d, 0, sizeof(struct dc_data));
307    
308          INTERRUPT_CONNECT(irq_path, d->irq);          INTERRUPT_CONNECT(irq_path, d->irq);
# Line 317  int dev_dc7085_init(struct machine *mach Line 318  int dev_dc7085_init(struct machine *mach
318          memory_device_register(mem, "dc7085", baseaddr, DEV_DC7085_LENGTH,          memory_device_register(mem, "dc7085", baseaddr, DEV_DC7085_LENGTH,
319              dev_dc7085_access, d, DM_DEFAULT, NULL);              dev_dc7085_access, d, DM_DEFAULT, NULL);
320          machine_add_tickfunction(machine, dev_dc7085_tick, d,          machine_add_tickfunction(machine, dev_dc7085_tick, d,
321              DC_TICK_SHIFT, 0.0);              DC_TICK_SHIFT);
322    
323          return d->console_handle;          return d->console_handle;
324  }  }
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