/[gxemul]/trunk/src/devices/dev_dc7085.c
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Contents of /trunk/src/devices/dev_dc7085.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 8812 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 /*
2 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_dc7085.c,v 1.60 2006/12/31 21:35:26 debug Exp $
29 *
30 * DC7085 serial controller, used in some DECstation models.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "console.h"
38 #include "cpu.h"
39 #include "devices.h"
40 #include "machine.h"
41 #include "memory.h"
42 #include "misc.h"
43
44 #include "dc7085.h"
45
46
47 #define DC_TICK_SHIFT 14
48
49 #define MAX_QUEUE_LEN 32768
50
51 struct dc_data {
52 struct dc7085regs regs;
53
54 int console_handle;
55
56 /* For slow_serial_interrupts_hack_for_linux: */
57 int just_transmitted_something;
58
59 unsigned char rx_queue_char[MAX_QUEUE_LEN];
60 char rx_queue_lineno[MAX_QUEUE_LEN];
61 int cur_rx_queue_pos_write;
62 int cur_rx_queue_pos_read;
63
64 int tx_scanner;
65
66 struct interrupt irq;
67 int use_fb;
68
69 struct lk201_data lk201;
70 };
71
72
73 /*
74 * Add a character to the receive queue.
75 */
76 void add_to_rx_queue(void *e, int ch, int line_no)
77 {
78 struct dc_data *d = (struct dc_data *) e;
79 int entries_in_use = d->cur_rx_queue_pos_write -
80 d->cur_rx_queue_pos_read;
81
82 while (entries_in_use < 0)
83 entries_in_use += MAX_QUEUE_LEN;
84
85 /* Ignore mouse updates, if they come too often: */
86 if (entries_in_use > MAX_QUEUE_LEN/2 && line_no == DCMOUSE_PORT)
87 return;
88
89 d->rx_queue_char[d->cur_rx_queue_pos_write] = ch;
90 d->rx_queue_lineno[d->cur_rx_queue_pos_write] = line_no;
91 d->cur_rx_queue_pos_write ++;
92 if (d->cur_rx_queue_pos_write == MAX_QUEUE_LEN)
93 d->cur_rx_queue_pos_write = 0;
94
95 if (d->cur_rx_queue_pos_write == d->cur_rx_queue_pos_read)
96 fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
97 }
98
99
100 DEVICE_TICK(dc7085)
101 {
102 /*
103 * If a key is available from the keyboard, add it to the rx queue.
104 * If other bits are set, an interrupt might need to be caused.
105 */
106 struct dc_data *d = extra;
107 int avail;
108
109 if (cpu->machine->slow_serial_interrupts_hack_for_linux) {
110 /*
111 * Special hack to prevent Linux from Oopsing. (This makes
112 * interrupts not come as fast as possible.)
113 */
114 if (d->just_transmitted_something) {
115 d->just_transmitted_something --;
116 return;
117 }
118 }
119
120 d->regs.dc_csr &= ~CSR_RDONE;
121
122 if ((d->regs.dc_csr & CSR_MSE) && !(d->regs.dc_csr & CSR_TRDY)) {
123 int scanner_start = d->tx_scanner;
124
125 /* Loop until we've checked all 4 channels, or some
126 channel was ready to transmit: */
127
128 do {
129 d->tx_scanner = (d->tx_scanner + 1) % 4;
130
131 if (d->regs.dc_tcr & (1 << d->tx_scanner)) {
132 d->regs.dc_csr |= CSR_TRDY;
133 if (d->regs.dc_csr & CSR_TIE)
134 INTERRUPT_ASSERT(d->irq);
135
136 d->regs.dc_csr &= ~CSR_TX_LINE_NUM;
137 d->regs.dc_csr |= (d->tx_scanner << 8);
138 }
139 } while (!(d->regs.dc_csr & CSR_TRDY) &&
140 d->tx_scanner != scanner_start);
141
142 /* We have to return here. NetBSD can handle both
143 rx and tx interrupts simultaneously, but Ultrix
144 doesn't like that? */
145
146 if (d->regs.dc_csr & CSR_TRDY)
147 return;
148 }
149
150 lk201_tick(cpu->machine, &d->lk201);
151
152 avail = d->cur_rx_queue_pos_write != d->cur_rx_queue_pos_read;
153
154 if (avail && (d->regs.dc_csr & CSR_MSE))
155 d->regs.dc_csr |= CSR_RDONE;
156
157 if ((d->regs.dc_csr & CSR_RDONE) && (d->regs.dc_csr & CSR_RIE))
158 INTERRUPT_ASSERT(d->irq);
159 }
160
161
162 DEVICE_ACCESS(dc7085)
163 {
164 uint64_t idata = 0, odata = 0;
165 size_t i;
166 struct dc_data *d = extra;
167
168 if (writeflag == MEM_WRITE)
169 idata = memory_readmax64(cpu, data, len);
170
171 /* Always clear: */
172 d->regs.dc_csr &= ~CSR_CLR;
173
174 switch (relative_addr) {
175 case 0x00: /* CSR: Control and Status */
176 if (writeflag == MEM_WRITE) {
177 debug("[ dc7085 write to CSR: 0x%04x ]\n", idata);
178 idata &= (CSR_TIE | CSR_RIE | CSR_MSE | CSR_CLR
179 | CSR_MAINT);
180 d->regs.dc_csr &= ~(CSR_TIE | CSR_RIE | CSR_MSE
181 | CSR_CLR | CSR_MAINT);
182 d->regs.dc_csr |= idata;
183 if (!(d->regs.dc_csr & CSR_MSE))
184 d->regs.dc_csr &= ~(CSR_TRDY | CSR_RDONE);
185 goto do_return;
186 } else {
187 /* read: */
188
189 /* fatal("[ dc7085 read from CSR: (csr = 0x%04x) ]\n",
190 d->regs.dc_csr); */
191 odata = d->regs.dc_csr;
192 }
193 break;
194 case 0x08: /* LPR: */
195 if (writeflag == MEM_WRITE) {
196 debug("[ dc7085 write to LPR: 0x%04x ]\n", idata);
197 d->regs.dc_rbuf_lpr = idata;
198 goto do_return;
199 } else {
200 /* read: */
201 int avail = d->cur_rx_queue_pos_write !=
202 d->cur_rx_queue_pos_read;
203 int ch = 0, lineno = 0;
204 /* debug("[ dc7085 read from RBUF: "); */
205 if (avail) {
206 ch = d->rx_queue_char[d->cur_rx_queue_pos_read];
207 lineno = d->rx_queue_lineno[
208 d->cur_rx_queue_pos_read];
209 d->cur_rx_queue_pos_read++;
210 if (d->cur_rx_queue_pos_read == MAX_QUEUE_LEN)
211 d->cur_rx_queue_pos_read = 0;
212 /* if (ch >= ' ' && ch < 127)
213 debug("'%c'", ch);
214 else
215 debug("0x%x", ch);
216 debug(" for lineno %i ", lineno); */
217 } /* else
218 debug("empty ");
219 debug("]\n"); */
220 odata = (avail? RBUF_DVAL:0) |
221 (lineno << RBUF_LINE_NUM_SHIFT) | ch;
222
223 d->regs.dc_csr &= ~CSR_RDONE;
224 INTERRUPT_DEASSERT(d->irq);
225
226 d->just_transmitted_something = 4;
227 }
228 break;
229 case 0x10: /* TCR: */
230 if (writeflag == MEM_WRITE) {
231 /* fatal("[ dc7085 write to TCR: 0x%04x) ]\n",
232 (int)idata); */
233 d->regs.dc_tcr = idata;
234 d->regs.dc_csr &= ~CSR_TRDY;
235 INTERRUPT_DEASSERT(d->irq);
236 goto do_return;
237 } else {
238 /* read: */
239 /* debug("[ dc7085 read from TCR: (tcr = 0x%04x) ]\n",
240 d->regs.dc_tcr); */
241 odata = d->regs.dc_tcr;
242 }
243 break;
244 case 0x18: /* Modem status (R), transmit data (W) */
245 if (writeflag == MEM_WRITE) {
246 int line_no = (d->regs.dc_csr >>
247 RBUF_LINE_NUM_SHIFT) & 0x3;
248 idata &= 0xff;
249
250 lk201_tx_data(&d->lk201, line_no, idata);
251
252 d->regs.dc_csr &= ~CSR_TRDY;
253 INTERRUPT_DEASSERT(d->irq);
254
255 d->just_transmitted_something = 4;
256 } else {
257 /* read: */
258 d->regs.dc_msr_tdr |= MSR_DSR2 | MSR_CD2 |
259 MSR_DSR3 | MSR_CD3;
260 debug("[ dc7085 read from MSR: (msr_tdr = 0x%04x) ]\n",
261 d->regs.dc_msr_tdr);
262 odata = d->regs.dc_msr_tdr;
263 }
264 break;
265 default:
266 if (writeflag==MEM_READ) {
267 debug("[ dc7085 read from 0x%08lx ]\n",
268 (long)relative_addr);
269 } else {
270 debug("[ dc7085 write to 0x%08lx:",
271 (long)relative_addr);
272 for (i=0; i<len; i++)
273 debug(" %02x", data[i]);
274 debug(" ]\n");
275 }
276 }
277
278 if (writeflag == MEM_READ)
279 memory_writemax64(cpu, data, len, odata);
280
281 do_return:
282 dev_dc7085_tick(cpu, extra);
283
284 return 1;
285 }
286
287
288 /*
289 * dev_dc7085_init():
290 *
291 * Initialize a dc7085 serial controller device. use_fb should be non-zero
292 * if a framebuffer device is used. Channel 0 will then be treated as a
293 * DECstation keyboard, instead of a plain serial console.
294 */
295 int dev_dc7085_init(struct machine *machine, struct memory *mem,
296 uint64_t baseaddr, char *irq_path, int use_fb)
297 {
298 struct dc_data *d;
299
300 d = malloc(sizeof(struct dc_data));
301 if (d == NULL) {
302 fprintf(stderr, "out of memory\n");
303 exit(1);
304 }
305 memset(d, 0, sizeof(struct dc_data));
306
307 INTERRUPT_CONNECT(irq_path, d->irq);
308 d->use_fb = use_fb;
309
310 d->regs.dc_csr = CSR_TRDY | CSR_MSE;
311 d->regs.dc_tcr = 0x00;
312
313 d->console_handle = console_start_slave(machine, "DC7085", 1);
314
315 lk201_init(&d->lk201, use_fb, add_to_rx_queue, d->console_handle, d);
316
317 memory_device_register(mem, "dc7085", baseaddr, DEV_DC7085_LENGTH,
318 dev_dc7085_access, d, DM_DEFAULT, NULL);
319 machine_add_tickfunction(machine, dev_dc7085_tick, d,
320 DC_TICK_SHIFT, 0.0);
321
322 return d->console_handle;
323 }
324
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