/[gxemul]/trunk/src/devices/dev_dc7085.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/devices/dev_dc7085.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8926 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 /*
2 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_dc7085.c,v 1.55 2006/03/04 12:38:47 debug Exp $
29 *
30 * DC7085 serial controller, used in some DECstation models.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "console.h"
38 #include "cpu.h"
39 #include "devices.h"
40 #include "machine.h"
41 #include "memory.h"
42 #include "misc.h"
43
44 #include "dc7085.h"
45
46
47 #define DC_TICK_SHIFT 14
48
49 #define MAX_QUEUE_LEN 4096
50
51 struct dc_data {
52 struct dc7085regs regs;
53
54 int console_handle;
55
56 /* For slow_serial_interrupts_hack_for_linux: */
57 int just_transmitted_something;
58
59 unsigned char rx_queue_char[MAX_QUEUE_LEN];
60 char rx_queue_lineno[MAX_QUEUE_LEN];
61 int cur_rx_queue_pos_write;
62 int cur_rx_queue_pos_read;
63
64 int tx_scanner;
65
66 int irqnr;
67 int use_fb;
68
69 struct lk201_data lk201;
70 };
71
72
73 /*
74 * Add a character to the receive queue.
75 */
76 void add_to_rx_queue(void *e, int ch, int line_no)
77 {
78 struct dc_data *d = (struct dc_data *) e;
79 int entries_in_use = d->cur_rx_queue_pos_write -
80 d->cur_rx_queue_pos_read;
81 while (entries_in_use < 0)
82 entries_in_use += MAX_QUEUE_LEN;
83
84 /* Ignore mouse updates, if they come too often: */
85 if (entries_in_use > MAX_QUEUE_LEN/2 && line_no == DCMOUSE_PORT)
86 return;
87
88 d->rx_queue_char[d->cur_rx_queue_pos_write] = ch;
89 d->rx_queue_lineno[d->cur_rx_queue_pos_write] = line_no;
90 d->cur_rx_queue_pos_write ++;
91 if (d->cur_rx_queue_pos_write == MAX_QUEUE_LEN)
92 d->cur_rx_queue_pos_write = 0;
93
94 if (d->cur_rx_queue_pos_write == d->cur_rx_queue_pos_read)
95 fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
96 }
97
98
99 /*
100 * dev_dc7085_tick():
101 *
102 * This function is called "every now and then".
103 * If a key is available from the keyboard, add it to the rx queue.
104 * If other bits are set, an interrupt might need to be caused.
105 */
106 void dev_dc7085_tick(struct cpu *cpu, void *extra)
107 {
108 struct dc_data *d = extra;
109 int avail;
110
111 if (cpu->machine->slow_serial_interrupts_hack_for_linux) {
112 /*
113 * Special hack to prevent Linux from Oopsing. (This makes
114 * interrupts not come as fast as possible.)
115 */
116 if (d->just_transmitted_something) {
117 d->just_transmitted_something --;
118 return;
119 }
120 }
121
122 d->regs.dc_csr &= ~CSR_RDONE;
123
124 if ((d->regs.dc_csr & CSR_MSE) && !(d->regs.dc_csr & CSR_TRDY)) {
125 int scanner_start = d->tx_scanner;
126
127 /* Loop until we've checked all 4 channels, or some
128 channel was ready to transmit: */
129
130 do {
131 d->tx_scanner = (d->tx_scanner + 1) % 4;
132
133 if (d->regs.dc_tcr & (1 << d->tx_scanner)) {
134 d->regs.dc_csr |= CSR_TRDY;
135 if (d->regs.dc_csr & CSR_TIE)
136 cpu_interrupt(cpu, d->irqnr);
137
138 d->regs.dc_csr &= ~CSR_TX_LINE_NUM;
139 d->regs.dc_csr |= (d->tx_scanner << 8);
140 }
141 } while (!(d->regs.dc_csr & CSR_TRDY) &&
142 d->tx_scanner != scanner_start);
143
144 /* We have to return here. NetBSD can handle both
145 rx and tx interrupts simultaneously, but Ultrix
146 doesn't like that? */
147
148 if (d->regs.dc_csr & CSR_TRDY)
149 return;
150 }
151
152 lk201_tick(&d->lk201);
153
154 avail = d->cur_rx_queue_pos_write != d->cur_rx_queue_pos_read;
155
156 if (avail && (d->regs.dc_csr & CSR_MSE))
157 d->regs.dc_csr |= CSR_RDONE;
158
159 if ((d->regs.dc_csr & CSR_RDONE) && (d->regs.dc_csr & CSR_RIE))
160 cpu_interrupt(cpu, d->irqnr);
161 }
162
163
164 /*
165 * dev_dc7085_access():
166 */
167 DEVICE_ACCESS(dc7085)
168 {
169 uint64_t idata = 0, odata = 0;
170 size_t i;
171 struct dc_data *d = extra;
172
173 if (writeflag == MEM_WRITE)
174 idata = memory_readmax64(cpu, data, len);
175
176 /* Always clear: */
177 d->regs.dc_csr &= ~CSR_CLR;
178
179 switch (relative_addr) {
180 case 0x00: /* CSR: Control and Status */
181 if (writeflag == MEM_WRITE) {
182 debug("[ dc7085 write to CSR: 0x%04x ]\n", idata);
183 idata &= (CSR_TIE | CSR_RIE | CSR_MSE | CSR_CLR
184 | CSR_MAINT);
185 d->regs.dc_csr &= ~(CSR_TIE | CSR_RIE | CSR_MSE
186 | CSR_CLR | CSR_MAINT);
187 d->regs.dc_csr |= idata;
188 if (!(d->regs.dc_csr & CSR_MSE))
189 d->regs.dc_csr &= ~(CSR_TRDY | CSR_RDONE);
190 goto do_return;
191 } else {
192 /* read: */
193
194 /* fatal("[ dc7085 read from CSR: (csr = 0x%04x) ]\n",
195 d->regs.dc_csr); */
196 odata = d->regs.dc_csr;
197 }
198 break;
199 case 0x08: /* LPR: */
200 if (writeflag == MEM_WRITE) {
201 debug("[ dc7085 write to LPR: 0x%04x ]\n", idata);
202 d->regs.dc_rbuf_lpr = idata;
203 goto do_return;
204 } else {
205 /* read: */
206 int avail = d->cur_rx_queue_pos_write !=
207 d->cur_rx_queue_pos_read;
208 int ch = 0, lineno = 0;
209 /* debug("[ dc7085 read from RBUF: "); */
210 if (avail) {
211 ch = d->rx_queue_char[d->cur_rx_queue_pos_read];
212 lineno = d->rx_queue_lineno[
213 d->cur_rx_queue_pos_read];
214 d->cur_rx_queue_pos_read++;
215 if (d->cur_rx_queue_pos_read == MAX_QUEUE_LEN)
216 d->cur_rx_queue_pos_read = 0;
217 /* if (ch >= ' ' && ch < 127)
218 debug("'%c'", ch);
219 else
220 debug("0x%x", ch);
221 debug(" for lineno %i ", lineno); */
222 } /* else
223 debug("empty ");
224 debug("]\n"); */
225 odata = (avail? RBUF_DVAL:0) |
226 (lineno << RBUF_LINE_NUM_SHIFT) | ch;
227
228 d->regs.dc_csr &= ~CSR_RDONE;
229 cpu_interrupt_ack(cpu, d->irqnr);
230
231 d->just_transmitted_something = 4;
232 }
233 break;
234 case 0x10: /* TCR: */
235 if (writeflag == MEM_WRITE) {
236 /* fatal("[ dc7085 write to TCR: 0x%04x) ]\n",
237 (int)idata); */
238 d->regs.dc_tcr = idata;
239 d->regs.dc_csr &= ~CSR_TRDY;
240 cpu_interrupt_ack(cpu, d->irqnr);
241 goto do_return;
242 } else {
243 /* read: */
244 /* debug("[ dc7085 read from TCR: (tcr = 0x%04x) ]\n",
245 d->regs.dc_tcr); */
246 odata = d->regs.dc_tcr;
247 }
248 break;
249 case 0x18: /* Modem status (R), transmit data (W) */
250 if (writeflag == MEM_WRITE) {
251 int line_no = (d->regs.dc_csr >>
252 RBUF_LINE_NUM_SHIFT) & 0x3;
253 idata &= 0xff;
254
255 lk201_tx_data(&d->lk201, line_no, idata);
256
257 d->regs.dc_csr &= ~CSR_TRDY;
258 cpu_interrupt_ack(cpu, d->irqnr);
259
260 d->just_transmitted_something = 4;
261 } else {
262 /* read: */
263 d->regs.dc_msr_tdr |= MSR_DSR2 | MSR_CD2 |
264 MSR_DSR3 | MSR_CD3;
265 debug("[ dc7085 read from MSR: (msr_tdr = 0x%04x) ]\n",
266 d->regs.dc_msr_tdr);
267 odata = d->regs.dc_msr_tdr;
268 }
269 break;
270 default:
271 if (writeflag==MEM_READ) {
272 debug("[ dc7085 read from 0x%08lx ]\n",
273 (long)relative_addr);
274 } else {
275 debug("[ dc7085 write to 0x%08lx:",
276 (long)relative_addr);
277 for (i=0; i<len; i++)
278 debug(" %02x", data[i]);
279 debug(" ]\n");
280 }
281 }
282
283 if (writeflag == MEM_READ)
284 memory_writemax64(cpu, data, len, odata);
285
286 do_return:
287 dev_dc7085_tick(cpu, extra);
288
289 return 1;
290 }
291
292
293 /*
294 * dev_dc7085_init():
295 *
296 * Initialize a dc7085 serial controller device. use_fb should be non-zero
297 * if a framebuffer device is used. Channel 0 will then be treated as a
298 * DECstation keyboard, instead of a plain serial console.
299 */
300 int dev_dc7085_init(struct machine *machine, struct memory *mem,
301 uint64_t baseaddr, int irq_nr, int use_fb)
302 {
303 struct dc_data *d;
304
305 d = malloc(sizeof(struct dc_data));
306 if (d == NULL) {
307 fprintf(stderr, "out of memory\n");
308 exit(1);
309 }
310 memset(d, 0, sizeof(struct dc_data));
311 d->irqnr = irq_nr;
312 d->use_fb = use_fb;
313
314 d->regs.dc_csr = CSR_TRDY | CSR_MSE;
315 d->regs.dc_tcr = 0x00;
316
317 d->console_handle = console_start_slave(machine, "DC7085", 1);
318
319 lk201_init(&d->lk201, use_fb, add_to_rx_queue, d->console_handle, d);
320
321 memory_device_register(mem, "dc7085", baseaddr, DEV_DC7085_LENGTH,
322 dev_dc7085_access, d, DM_DEFAULT, NULL);
323 machine_add_tickfunction(machine, dev_dc7085_tick, d,
324 DC_TICK_SHIFT, 0.0);
325
326 return d->console_handle;
327 }
328

  ViewVC Help
Powered by ViewVC 1.1.26