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/* |
/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_dc7085.c,v 1.56 2006/07/23 14:37:34 debug Exp $ |
* $Id: dev_dc7085.c,v 1.60 2006/12/31 21:35:26 debug Exp $ |
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* |
* |
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* DC7085 serial controller, used in some DECstation models. |
* DC7085 serial controller, used in some DECstation models. |
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*/ |
*/ |
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#define DC_TICK_SHIFT 14 |
#define DC_TICK_SHIFT 14 |
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#define MAX_QUEUE_LEN 4096 |
#define MAX_QUEUE_LEN 32768 |
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struct dc_data { |
struct dc_data { |
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struct dc7085regs regs; |
struct dc7085regs regs; |
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int tx_scanner; |
int tx_scanner; |
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int irqnr; |
struct interrupt irq; |
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int use_fb; |
int use_fb; |
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struct lk201_data lk201; |
struct lk201_data lk201; |
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struct dc_data *d = (struct dc_data *) e; |
struct dc_data *d = (struct dc_data *) e; |
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int entries_in_use = d->cur_rx_queue_pos_write - |
int entries_in_use = d->cur_rx_queue_pos_write - |
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d->cur_rx_queue_pos_read; |
d->cur_rx_queue_pos_read; |
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while (entries_in_use < 0) |
while (entries_in_use < 0) |
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entries_in_use += MAX_QUEUE_LEN; |
entries_in_use += MAX_QUEUE_LEN; |
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if (d->regs.dc_tcr & (1 << d->tx_scanner)) { |
if (d->regs.dc_tcr & (1 << d->tx_scanner)) { |
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d->regs.dc_csr |= CSR_TRDY; |
d->regs.dc_csr |= CSR_TRDY; |
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if (d->regs.dc_csr & CSR_TIE) |
if (d->regs.dc_csr & CSR_TIE) |
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cpu_interrupt(cpu, d->irqnr); |
INTERRUPT_ASSERT(d->irq); |
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d->regs.dc_csr &= ~CSR_TX_LINE_NUM; |
d->regs.dc_csr &= ~CSR_TX_LINE_NUM; |
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d->regs.dc_csr |= (d->tx_scanner << 8); |
d->regs.dc_csr |= (d->tx_scanner << 8); |
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return; |
return; |
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} |
} |
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lk201_tick(&d->lk201); |
lk201_tick(cpu->machine, &d->lk201); |
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avail = d->cur_rx_queue_pos_write != d->cur_rx_queue_pos_read; |
avail = d->cur_rx_queue_pos_write != d->cur_rx_queue_pos_read; |
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d->regs.dc_csr |= CSR_RDONE; |
d->regs.dc_csr |= CSR_RDONE; |
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if ((d->regs.dc_csr & CSR_RDONE) && (d->regs.dc_csr & CSR_RIE)) |
if ((d->regs.dc_csr & CSR_RDONE) && (d->regs.dc_csr & CSR_RIE)) |
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cpu_interrupt(cpu, d->irqnr); |
INTERRUPT_ASSERT(d->irq); |
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} |
} |
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(lineno << RBUF_LINE_NUM_SHIFT) | ch; |
(lineno << RBUF_LINE_NUM_SHIFT) | ch; |
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d->regs.dc_csr &= ~CSR_RDONE; |
d->regs.dc_csr &= ~CSR_RDONE; |
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cpu_interrupt_ack(cpu, d->irqnr); |
INTERRUPT_DEASSERT(d->irq); |
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d->just_transmitted_something = 4; |
d->just_transmitted_something = 4; |
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} |
} |
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(int)idata); */ |
(int)idata); */ |
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d->regs.dc_tcr = idata; |
d->regs.dc_tcr = idata; |
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d->regs.dc_csr &= ~CSR_TRDY; |
d->regs.dc_csr &= ~CSR_TRDY; |
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cpu_interrupt_ack(cpu, d->irqnr); |
INTERRUPT_DEASSERT(d->irq); |
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goto do_return; |
goto do_return; |
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} else { |
} else { |
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/* read: */ |
/* read: */ |
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lk201_tx_data(&d->lk201, line_no, idata); |
lk201_tx_data(&d->lk201, line_no, idata); |
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d->regs.dc_csr &= ~CSR_TRDY; |
d->regs.dc_csr &= ~CSR_TRDY; |
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cpu_interrupt_ack(cpu, d->irqnr); |
INTERRUPT_DEASSERT(d->irq); |
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d->just_transmitted_something = 4; |
d->just_transmitted_something = 4; |
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} else { |
} else { |
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* DECstation keyboard, instead of a plain serial console. |
* DECstation keyboard, instead of a plain serial console. |
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*/ |
*/ |
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int dev_dc7085_init(struct machine *machine, struct memory *mem, |
int dev_dc7085_init(struct machine *machine, struct memory *mem, |
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uint64_t baseaddr, int irq_nr, int use_fb) |
uint64_t baseaddr, char *irq_path, int use_fb) |
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{ |
{ |
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struct dc_data *d; |
struct dc_data *d; |
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exit(1); |
exit(1); |
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} |
} |
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memset(d, 0, sizeof(struct dc_data)); |
memset(d, 0, sizeof(struct dc_data)); |
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d->irqnr = irq_nr; |
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INTERRUPT_CONNECT(irq_path, d->irq); |
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d->use_fb = use_fb; |
d->use_fb = use_fb; |
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d->regs.dc_csr = CSR_TRDY | CSR_MSE; |
d->regs.dc_csr = CSR_TRDY | CSR_MSE; |