/[gxemul]/trunk/src/devices/dev_bebox.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Diff of /trunk/src/devices/dev_bebox.c

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revision 4 by dpavlin, Mon Oct 8 16:18:00 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_bebox.c,v 1.3 2005/02/23 22:08:19 debug Exp $   *  $Id: dev_bebox.c,v 1.9 2006/02/09 20:02:59 debug Exp $
29   *   *
30   *  Emulation of BeBox motherboard registers. See the following URL for more   *  Emulation of BeBox motherboard registers. See the following URL for more
31   *  information:   *  information:
# Line 39  Line 39 
39    
40  #include "cpu.h"  #include "cpu.h"
41  #include "device.h"  #include "device.h"
42    #include "devices.h"
43  #include "machine.h"  #include "machine.h"
44  #include "memory.h"  #include "memory.h"
45  #include "misc.h"  #include "misc.h"
46    
47    
48  struct bebox_data {  /*
49          /*  The 5 motherboard registers:  */   *  check_cpu_masks():
50          uint32_t        cpu0_intmask;   *
51          uint32_t        cpu1_intmask;   *  BeBox interrupt enable bits are not allowed to be present in
52          uint32_t        int_source;   *  both CPUs at the same time.
53          uint32_t        xpi;   */
54          uint32_t        resets;  static void check_cpu_masks(struct cpu *cpu, struct bebox_data *d)
55  };  {
56            d->cpu0_int_mask &= 0x7fffffff;
57            d->cpu1_int_mask &= 0x7fffffff;
58            if ((d->cpu0_int_mask | d->cpu1_int_mask) !=
59                (d->cpu0_int_mask ^ d->cpu1_int_mask))
60                    fatal("check_cpu_masks(): BeBox cpu int masks"
61                        " collide!\n");
62    }
63    
64    
65  /*  /*
66   *  dev_bebox_access():   *  dev_bebox_access():
67   */   */
68  int dev_bebox_access(struct cpu *cpu, struct memory *mem,  DEVICE_ACCESS(bebox)
         uint64_t relative_addr, unsigned char *data, size_t len, int writeflag,  
         void *extra)  
69  {  {
70          struct bebox_data *d = extra;          struct bebox_data *d = extra;
71          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
72    
73          idata = memory_readmax64(cpu, data, len);          if (writeflag == MEM_WRITE)
74                    idata = memory_readmax64(cpu, data, len);
75    
76          switch (relative_addr) {          switch (relative_addr) {
77    
78            case 0x0f0:
79                    if (writeflag == MEM_READ)
80                            odata = d->cpu0_int_mask;
81                    else {
82                            if (idata & 0x80000000)
83                                    d->cpu0_int_mask |= idata;
84                            else
85                                    d->cpu0_int_mask &= ~idata;
86                            check_cpu_masks(cpu, d);
87                    }
88                    break;
89    
90            case 0x1f0:
91                    if (writeflag == MEM_READ)
92                            odata = d->cpu1_int_mask;
93                    else {
94                            if (idata & 0x80000000)
95                                    d->cpu1_int_mask |= idata;
96                            else
97                                    d->cpu1_int_mask &= ~idata;
98                            check_cpu_masks(cpu, d);
99                    }
100                    break;
101    
102            case 0x2f0:
103                    if (writeflag == MEM_READ)
104                            odata = d->int_status;
105                    else {
106                            if (idata & 0x80000000)
107                                    d->int_status |= idata;
108                            else
109                                    d->int_status &= ~idata;
110                            d->int_status &= 0x7fffffff;
111                    }
112                    break;
113    
114          case 0x3f0:          case 0x3f0:
115                  if (writeflag == MEM_READ) {                  if (writeflag == MEM_READ) {
116                          odata = d->xpi;                          odata = d->xpi;
# Line 97  int dev_bebox_access(struct cpu *cpu, st Line 141  int dev_bebox_access(struct cpu *cpu, st
141  }  }
142    
143    
144  /*  DEVINIT(bebox)
  *  devinit_bebox():  
  */  
 int devinit_bebox(struct devinit *devinit)  
145  {  {
146          struct bebox_data *d;          struct bebox_data *d;
147    
# Line 112  int devinit_bebox(struct devinit *devini Line 153  int devinit_bebox(struct devinit *devini
153          memset(d, 0, sizeof(struct bebox_data));          memset(d, 0, sizeof(struct bebox_data));
154    
155          memory_device_register(devinit->machine->memory, devinit->name,          memory_device_register(devinit->machine->memory, devinit->name,
156              0x7ffff000, 0x500, dev_bebox_access, d, MEM_DEFAULT, NULL);              0x7ffff000, 0x500, dev_bebox_access, d, DM_DEFAULT, NULL);
157    
158            devinit->return_ptr = d;
159    
160          return 1;          return 1;
161  }  }
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