25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_bebox.c,v 1.4 2005/10/26 14:37:03 debug Exp $ |
* $Id: dev_bebox.c,v 1.7 2005/11/16 21:15:18 debug Exp $ |
29 |
* |
* |
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* Emulation of BeBox motherboard registers. See the following URL for more |
* Emulation of BeBox motherboard registers. See the following URL for more |
31 |
* information: |
* information: |
39 |
|
|
40 |
#include "cpu.h" |
#include "cpu.h" |
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#include "device.h" |
#include "device.h" |
42 |
|
#include "devices.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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|
|
47 |
|
|
48 |
struct bebox_data { |
/* |
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/* The 5 motherboard registers: */ |
* check_cpu_masks(): |
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uint32_t cpu0_intmask; |
* |
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uint32_t cpu1_intmask; |
* BeBox interrupt enable bits are not allowed to be present in |
52 |
uint32_t int_source; |
* both CPUs at the same time. |
53 |
uint32_t xpi; |
*/ |
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uint32_t resets; |
static void check_cpu_masks(struct cpu *cpu, struct bebox_data *d) |
55 |
}; |
{ |
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|
d->cpu0_int_mask &= 0x7fffffff; |
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d->cpu1_int_mask &= 0x7fffffff; |
58 |
|
if ((d->cpu0_int_mask | d->cpu1_int_mask) != |
59 |
|
(d->cpu0_int_mask ^ d->cpu1_int_mask)) |
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fatal("check_cpu_masks(): BeBox cpu int masks" |
61 |
|
" collide!\n"); |
62 |
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} |
63 |
|
|
64 |
|
|
65 |
/* |
/* |
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idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
77 |
|
|
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switch (relative_addr) { |
switch (relative_addr) { |
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|
|
80 |
|
case 0x0f0: |
81 |
|
if (writeflag == MEM_READ) |
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|
odata = d->cpu0_int_mask; |
83 |
|
else { |
84 |
|
if (idata & 0x80000000) |
85 |
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d->cpu0_int_mask |= idata; |
86 |
|
else |
87 |
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d->cpu0_int_mask &= ~idata; |
88 |
|
check_cpu_masks(cpu, d); |
89 |
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} |
90 |
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break; |
91 |
|
|
92 |
|
case 0x1f0: |
93 |
|
if (writeflag == MEM_READ) |
94 |
|
odata = d->cpu1_int_mask; |
95 |
|
else { |
96 |
|
if (idata & 0x80000000) |
97 |
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d->cpu1_int_mask |= idata; |
98 |
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else |
99 |
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d->cpu1_int_mask &= ~idata; |
100 |
|
check_cpu_masks(cpu, d); |
101 |
|
} |
102 |
|
break; |
103 |
|
|
104 |
|
case 0x2f0: |
105 |
|
if (writeflag == MEM_READ) |
106 |
|
odata = d->int_status; |
107 |
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else { |
108 |
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if (idata & 0x80000000) |
109 |
|
d->int_status |= idata; |
110 |
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else |
111 |
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d->int_status &= ~idata; |
112 |
|
d->int_status &= 0x7fffffff; |
113 |
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} |
114 |
|
break; |
115 |
|
|
116 |
case 0x3f0: |
case 0x3f0: |
117 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
118 |
odata = d->xpi; |
odata = d->xpi; |
158 |
memset(d, 0, sizeof(struct bebox_data)); |
memset(d, 0, sizeof(struct bebox_data)); |
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|
|
160 |
memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
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0x7ffff000, 0x500, dev_bebox_access, d, MEM_DEFAULT, NULL); |
0x7ffff000, 0x500, dev_bebox_access, d, DM_DEFAULT, NULL); |
162 |
|
|
163 |
|
devinit->return_ptr = d; |
164 |
|
|
165 |
return 1; |
return 1; |
166 |
} |
} |