/[gxemul]/trunk/src/devices/dev_au1x00.c
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Contents of /trunk/src/devices/dev_au1x00.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 11350 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 /*
2 * Copyright (C) 2004-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_au1x00.c,v 1.22 2007/01/28 14:40:54 debug Exp $
29 *
30 * Au1x00 (eg Au1500) pseudo device. See aureg.h for bitfield details.
31 *
32 * Used in at least the MeshCube (Au1500) and on PB1000 (evbmips) boards.
33 *
34 * This is basically just a huge TODO. :-)
35 */
36
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <string.h>
40
41 #include "console.h"
42 #include "cpu.h"
43 #include "device.h"
44 #include "machine.h"
45 #include "memory.h"
46 #include "misc.h"
47
48 #include "aureg.h"
49
50
51 struct au1x00_ic_data {
52 int ic_nr;
53 uint32_t request0_int;
54 uint32_t request1_int;
55 uint32_t config0;
56 uint32_t config1;
57 uint32_t config2;
58 uint32_t source;
59 uint32_t assign_request;
60 uint32_t wakeup;
61 uint32_t mask;
62 };
63
64 struct au1x00_uart_data {
65 int console_handle;
66 int uart_nr;
67 int irq_nr;
68 int in_use;
69 uint32_t int_enable;
70 uint32_t modem_control;
71 };
72
73
74 struct au1x00_pc_data {
75 uint32_t reg[PC_SIZE/4 + 2];
76 int irq_nr;
77 };
78
79
80 #if 0
81 /* TODO: Convert this to the new interrupt syntax */
82 /*
83 * Au1x00 interrupt routine:
84 *
85 * TODO: This is just bogus so far. For more info, read this:
86 * http://www.meshcube.org/cgi-bin/viewcvs.cgi/kernel/linux/arch/
87 * mips/au1000/common/
88 *
89 * CPU int 2 = IC 0, request 0
90 * CPU int 3 = IC 0, request 1
91 * CPU int 4 = IC 1, request 0
92 * CPU int 5 = IC 1, request 1
93 *
94 * Interrupts 0..31 are on interrupt controller 0, interrupts 32..63 are
95 * on controller 1.
96 *
97 * Special case: if irq_nr == 64+8, then this just updates the CPU
98 * interrupt assertions.
99 */
100 void au1x00_interrupt(struct machine *m, struct cpu *cpu,
101 int irq_nr, int assrt)
102 {
103 uint32_t ms;
104
105 irq_nr -= 8;
106 debug("au1x00_interrupt(): irq_nr=%i assrt=%i\n", irq_nr, assrt);
107
108 if (irq_nr < 64) {
109 ms = 1 << (irq_nr & 31);
110
111 fatal("TODO: legacy interrupt rewrite!\n");
112 abort();
113
114 // if (assrt)
115 // m->md_int.au1x00_ic_data->request0_int |= ms;
116 // else
117 // m->md_int.au1x00_ic_data->request0_int &= ~ms;
118
119 /* TODO: Controller 1 */
120 }
121
122 fatal("TODO: legacy interrupt rewrite!\n");
123 abort();
124
125 // if ((m->md_int.au1x00_ic_data->request0_int &
126 // m->md_int.au1x00_ic_data->mask) != 0)
127 // cpu_interrupt(cpu, 2);
128 // else
129 // cpu_interrupt_ack(cpu, 2);
130
131 /* TODO: What _is_ request1? */
132
133 /* TODO: Controller 1 */
134 }
135 #endif
136
137
138 /*
139 * dev_au1x00_ic_access():
140 *
141 * Interrupt Controller.
142 */
143 DEVICE_ACCESS(au1x00_ic)
144 {
145 struct au1x00_ic_data *d = extra;
146 uint64_t idata = 0, odata = 0;
147
148 if (writeflag == MEM_WRITE)
149 idata = memory_readmax64(cpu, data, len);
150
151 /* TODO */
152
153 switch (relative_addr) {
154 case IC_CONFIG0_READ: /* READ or SET */
155 if (writeflag == MEM_READ)
156 odata = d->config0;
157 else
158 d->config0 |= idata;
159 break;
160 case IC_CONFIG0_CLEAR:
161 if (writeflag == MEM_READ)
162 odata = d->config0;
163 else
164 d->config0 &= ~idata;
165 break;
166 case IC_CONFIG1_READ: /* READ or SET */
167 if (writeflag == MEM_READ)
168 odata = d->config1;
169 else
170 d->config1 |= idata;
171 break;
172 case IC_CONFIG1_CLEAR:
173 if (writeflag == MEM_READ)
174 odata = d->config1;
175 else
176 d->config1 &= ~idata;
177 break;
178 case IC_CONFIG2_READ: /* READ or SET */
179 if (writeflag == MEM_READ)
180 odata = d->config2;
181 else
182 d->config2 |= idata;
183 break;
184 case IC_CONFIG2_CLEAR: /* or IC_REQUEST0_INT */
185 if (writeflag == MEM_READ)
186 odata = d->request0_int;
187 else
188 d->config2 &= ~idata;
189 break;
190 case IC_SOURCE_READ: /* READ or SET */
191 if (writeflag == MEM_READ)
192 odata = d->source;
193 else
194 d->source |= idata;
195 break;
196 case IC_SOURCE_CLEAR: /* or IC_REQUEST1_INT */
197 if (writeflag == MEM_READ)
198 odata = d->request1_int;
199 else
200 d->source &= ~idata;
201 break;
202 case IC_ASSIGN_REQUEST_READ: /* READ or SET */
203 if (writeflag == MEM_READ)
204 odata = d->assign_request;
205 else
206 d->assign_request |= idata;
207 break;
208 case IC_ASSIGN_REQUEST_CLEAR:
209 if (writeflag == MEM_READ)
210 odata = d->assign_request;
211 else
212 d->assign_request &= ~idata;
213 break;
214 case IC_WAKEUP_READ: /* READ or SET */
215 if (writeflag == MEM_READ)
216 odata = d->wakeup;
217 else
218 d->wakeup |= idata;
219 break;
220 case IC_WAKEUP_CLEAR:
221 if (writeflag == MEM_READ)
222 odata = d->wakeup;
223 else
224 d->wakeup &= ~idata;
225 break;
226 case IC_MASK_READ: /* READ or SET */
227 if (writeflag == MEM_READ)
228 odata = d->mask;
229 else
230 d->mask |= idata;
231 break;
232 case IC_MASK_CLEAR:
233 if (writeflag == MEM_READ)
234 odata = d->mask;
235 else
236 d->mask &= ~idata;
237 break;
238 default:
239 if (writeflag == MEM_READ) {
240 debug("[ au1x00_ic%i: read from 0x%08lx: 0x%08x ]\n",
241 d->ic_nr, (long)relative_addr, odata);
242 } else {
243 debug("[ au1x00_ic%i: write to 0x%08lx: 0x%08x ]\n",
244 d->ic_nr, (long)relative_addr, idata);
245 }
246 }
247
248 fatal("TODO: legacy interrupt rewrite!\n");
249 abort();
250
251 // if (writeflag == MEM_WRITE)
252 // cpu_interrupt(cpu, 8 + 64);
253
254 if (writeflag == MEM_READ)
255 memory_writemax64(cpu, data, len, odata);
256
257 return 1;
258 }
259
260
261 /*
262 * dev_au1x00_uart_access():
263 *
264 * UART (Serial controllers).
265 */
266 DEVICE_ACCESS(au1x00_uart)
267 {
268 struct au1x00_uart_data *d = extra;
269 uint64_t idata = 0, odata = 0;
270
271 if (writeflag == MEM_WRITE)
272 idata = memory_readmax64(cpu, data, len);
273
274 switch (relative_addr) {
275 case UART_RXDATA: /* 0x00 */
276 odata = console_readchar(d->console_handle);
277 break;
278 case UART_TXDATA: /* 0x04 */
279 console_putchar(d->console_handle, idata);
280 break;
281 case UART_INTERRUPT_ENABLE: /* 0x08 */
282 if (writeflag == MEM_READ)
283 odata = d->int_enable;
284 else
285 d->int_enable = idata;
286 break;
287 case UART_MODEM_CONTROL: /* 0x18 */
288 if (writeflag == MEM_READ)
289 odata = d->modem_control;
290 else
291 d->modem_control = idata;
292 break;
293 case UART_LINE_STATUS: /* 0x1c */
294 odata = ULS_TE + ULS_TFE;
295 if (console_charavail(d->console_handle))
296 odata |= ULS_DR;
297 break;
298 case UART_CLOCK_DIVIDER: /* 0x28 */
299 break;
300 default:
301 if (writeflag == MEM_READ) {
302 debug("[ au1x00_uart%i: read from 0x%08lx ]\n",
303 d->uart_nr, (long)relative_addr);
304 } else {
305 debug("[ au1x00_uart%i: write to 0x%08lx: 0x%08llx"
306 " ]\n", d->uart_nr, (long)relative_addr,
307 (long long)idata);
308 }
309 }
310
311 if (writeflag == MEM_READ)
312 memory_writemax64(cpu, data, len, odata);
313
314 return 1;
315 }
316
317
318 DEVICE_TICK(au1x00_pc)
319 {
320 /* struct au1x00_pc_data *d = extra; */
321
322 /* Periodic ticks at 32768 Hz? TODO */
323
324 fatal("TODO: legacy interrupt rewrite!\n");
325 abort();
326
327 // if (d->reg[PC_COUNTER_CONTROL/4] & CC_EN1)
328 // cpu_interrupt(cpu, 8 + d->irq_nr);
329 }
330
331
332 /*
333 * dev_au1x00_pc_access():
334 *
335 * Programmable Counters.
336 */
337 DEVICE_ACCESS(au1x00_pc)
338 {
339 struct au1x00_pc_data *d = extra;
340 uint64_t idata = 0, odata = 0;
341
342 if (writeflag == MEM_WRITE)
343 idata = memory_readmax64(cpu, data, len);
344
345 if (writeflag == MEM_READ)
346 odata = d->reg[relative_addr / sizeof(uint32_t)];
347 else
348 d->reg[relative_addr / sizeof(uint32_t)] = idata;
349
350 switch (relative_addr) {
351 default:
352 if (writeflag == MEM_READ) {
353 debug("[ au1x00_pc: read from 0x%08lx: 0x%08x ]\n",
354 (long)relative_addr, odata);
355 } else {
356 debug("[ au1x00_pc: write to 0x%08lx: 0x%08x ]\n",
357 (long)relative_addr, idata);
358 }
359 }
360
361 if (writeflag == MEM_READ)
362 memory_writemax64(cpu, data, len, odata);
363
364 return 1;
365 }
366
367
368 DEVINIT(au1x00)
369 {
370 struct machine *machine = devinit->machine;
371 struct au1x00_ic_data *d_ic0;
372 struct au1x00_ic_data *d_ic1;
373 struct au1x00_uart_data *d0;
374 struct au1x00_uart_data *d1;
375 struct au1x00_uart_data *d2;
376 struct au1x00_uart_data *d3;
377 struct au1x00_pc_data *d_pc;
378
379 d_ic0 = malloc(sizeof(struct au1x00_ic_data));
380 d_ic1 = malloc(sizeof(struct au1x00_ic_data));
381 d0 = malloc(sizeof(struct au1x00_uart_data));
382 d1 = malloc(sizeof(struct au1x00_uart_data));
383 d2 = malloc(sizeof(struct au1x00_uart_data));
384 d3 = malloc(sizeof(struct au1x00_uart_data));
385 d_pc = malloc(sizeof(struct au1x00_pc_data));
386
387 if (d0 == NULL || d1 == NULL || d2 == NULL ||
388 d3 == NULL || d_pc == NULL || d_ic0 == NULL
389 || d_ic1 == NULL) {
390 fprintf(stderr, "out of memory\n");
391 exit(1);
392 }
393 memset(d_ic0, 0, sizeof(struct au1x00_ic_data));
394 memset(d_ic1, 0, sizeof(struct au1x00_ic_data));
395 memset(d0, 0, sizeof(struct au1x00_uart_data));
396 memset(d1, 0, sizeof(struct au1x00_uart_data));
397 memset(d2, 0, sizeof(struct au1x00_uart_data));
398 memset(d3, 0, sizeof(struct au1x00_uart_data));
399 memset(d_pc, 0, sizeof(struct au1x00_pc_data));
400
401 d_ic0->ic_nr = 0;
402 d_ic1->ic_nr = 1;
403
404 d0->uart_nr = 0; d0->irq_nr = 0;
405 d1->uart_nr = 1; d1->irq_nr = 1;
406 d2->uart_nr = 2; d2->irq_nr = 2;
407 d3->uart_nr = 3; d3->irq_nr = 3;
408
409 /* Only allow input on the first UART, by default: */
410 d0->console_handle = console_start_slave(machine, "AU1x00 port 0", 1);
411 d1->console_handle = console_start_slave(machine, "AU1x00 port 1", 0);
412 d2->console_handle = console_start_slave(machine, "AU1x00 port 2", 0);
413 d3->console_handle = console_start_slave(machine, "AU1x00 port 3", 0);
414 d0->in_use = 1;
415 d1->in_use = 0;
416 d2->in_use = 0;
417 d3->in_use = 0;
418
419 d_pc->irq_nr = 14;
420
421 memory_device_register(machine->memory, "au1x00_ic0",
422 IC0_BASE, 0x100, dev_au1x00_ic_access, d_ic0, DM_DEFAULT, NULL);
423 memory_device_register(machine->memory, "au1x00_ic1",
424 IC1_BASE, 0x100, dev_au1x00_ic_access, d_ic1, DM_DEFAULT, NULL);
425
426 memory_device_register(machine->memory, "au1x00_uart0", UART0_BASE,
427 UART_SIZE, dev_au1x00_uart_access, d0, DM_DEFAULT, NULL);
428 memory_device_register(machine->memory, "au1x00_uart1", UART1_BASE,
429 UART_SIZE, dev_au1x00_uart_access, d1, DM_DEFAULT, NULL);
430 memory_device_register(machine->memory, "au1x00_uart2", UART2_BASE,
431 UART_SIZE, dev_au1x00_uart_access, d2, DM_DEFAULT, NULL);
432 memory_device_register(machine->memory, "au1x00_uart3", UART3_BASE,
433 UART_SIZE, dev_au1x00_uart_access, d3, DM_DEFAULT, NULL);
434
435 memory_device_register(machine->memory, "au1x00_pc", PC_BASE,
436 PC_SIZE+0x8, dev_au1x00_pc_access, d_pc, DM_DEFAULT, NULL);
437 machine_add_tickfunction(machine, dev_au1x00_pc_tick, d_pc, 15, 0.0);
438
439 return 1;
440 }
441

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