/[gxemul]/trunk/src/devices/dev_au1x00.c
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Contents of /trunk/src/devices/dev_au1x00.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 9768 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_au1x00.c,v 1.16 2006/01/01 13:17:16 debug Exp $
29 *
30 * Au1x00 (eg Au1500) pseudo device. See aureg.h for bitfield details.
31 *
32 * Used in at least the MeshCube (Au1500) and on PB1000 (evbmips) boards.
33 *
34 * This is basically just a huge TODO. :-)
35 */
36
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <string.h>
40
41 #include "console.h"
42 #include "cpu.h"
43 #include "devices.h"
44 #include "machine.h"
45 #include "memory.h"
46 #include "misc.h"
47
48 #include "aureg.h"
49
50
51 struct au1x00_uart_data {
52 int console_handle;
53 int uart_nr;
54 int irq_nr;
55 int in_use;
56 uint32_t int_enable;
57 uint32_t modem_control;
58 };
59
60
61 struct au1x00_pc_data {
62 uint32_t reg[PC_SIZE/4 + 2];
63 int irq_nr;
64 };
65
66
67 /*
68 * dev_au1x00_ic_access():
69 *
70 * Interrupt Controller.
71 */
72 DEVICE_ACCESS(au1x00_ic)
73 {
74 struct au1x00_ic_data *d = extra;
75 uint64_t idata = 0, odata = 0;
76
77 if (writeflag == MEM_WRITE)
78 idata = memory_readmax64(cpu, data, len);
79
80 /* TODO */
81
82 switch (relative_addr) {
83 case IC_CONFIG0_READ: /* READ or SET */
84 if (writeflag == MEM_READ)
85 odata = d->config0;
86 else
87 d->config0 |= idata;
88 break;
89 case IC_CONFIG0_CLEAR:
90 if (writeflag == MEM_READ)
91 odata = d->config0;
92 else
93 d->config0 &= ~idata;
94 break;
95 case IC_CONFIG1_READ: /* READ or SET */
96 if (writeflag == MEM_READ)
97 odata = d->config1;
98 else
99 d->config1 |= idata;
100 break;
101 case IC_CONFIG1_CLEAR:
102 if (writeflag == MEM_READ)
103 odata = d->config1;
104 else
105 d->config1 &= ~idata;
106 break;
107 case IC_CONFIG2_READ: /* READ or SET */
108 if (writeflag == MEM_READ)
109 odata = d->config2;
110 else
111 d->config2 |= idata;
112 break;
113 case IC_CONFIG2_CLEAR: /* or IC_REQUEST0_INT */
114 if (writeflag == MEM_READ)
115 odata = d->request0_int;
116 else
117 d->config2 &= ~idata;
118 break;
119 case IC_SOURCE_READ: /* READ or SET */
120 if (writeflag == MEM_READ)
121 odata = d->source;
122 else
123 d->source |= idata;
124 break;
125 case IC_SOURCE_CLEAR: /* or IC_REQUEST1_INT */
126 if (writeflag == MEM_READ)
127 odata = d->request1_int;
128 else
129 d->source &= ~idata;
130 break;
131 case IC_ASSIGN_REQUEST_READ: /* READ or SET */
132 if (writeflag == MEM_READ)
133 odata = d->assign_request;
134 else
135 d->assign_request |= idata;
136 break;
137 case IC_ASSIGN_REQUEST_CLEAR:
138 if (writeflag == MEM_READ)
139 odata = d->assign_request;
140 else
141 d->assign_request &= ~idata;
142 break;
143 case IC_WAKEUP_READ: /* READ or SET */
144 if (writeflag == MEM_READ)
145 odata = d->wakeup;
146 else
147 d->wakeup |= idata;
148 break;
149 case IC_WAKEUP_CLEAR:
150 if (writeflag == MEM_READ)
151 odata = d->wakeup;
152 else
153 d->wakeup &= ~idata;
154 break;
155 case IC_MASK_READ: /* READ or SET */
156 if (writeflag == MEM_READ)
157 odata = d->mask;
158 else
159 d->mask |= idata;
160 break;
161 case IC_MASK_CLEAR:
162 if (writeflag == MEM_READ)
163 odata = d->mask;
164 else
165 d->mask &= ~idata;
166 break;
167 default:
168 if (writeflag == MEM_READ) {
169 debug("[ au1x00_ic%i: read from 0x%08lx: 0x%08x ]\n",
170 d->ic_nr, (long)relative_addr, odata);
171 } else {
172 debug("[ au1x00_ic%i: write to 0x%08lx: 0x%08x ]\n",
173 d->ic_nr, (long)relative_addr, idata);
174 }
175 }
176
177 if (writeflag == MEM_WRITE)
178 cpu_interrupt(cpu, 8 + 64);
179
180 if (writeflag == MEM_READ)
181 memory_writemax64(cpu, data, len, odata);
182
183 return 1;
184 }
185
186
187 /*
188 * dev_au1x00_uart_access():
189 *
190 * UART (Serial controllers).
191 */
192 DEVICE_ACCESS(au1x00_uart)
193 {
194 struct au1x00_uart_data *d = extra;
195 uint64_t idata = 0, odata = 0;
196
197 if (writeflag == MEM_WRITE)
198 idata = memory_readmax64(cpu, data, len);
199
200 switch (relative_addr) {
201 case UART_RXDATA: /* 0x00 */
202 odata = console_readchar(d->console_handle);
203 break;
204 case UART_TXDATA: /* 0x04 */
205 console_putchar(d->console_handle, idata);
206 break;
207 case UART_INTERRUPT_ENABLE: /* 0x08 */
208 if (writeflag == MEM_READ)
209 odata = d->int_enable;
210 else
211 d->int_enable = idata;
212 break;
213 case UART_MODEM_CONTROL: /* 0x18 */
214 if (writeflag == MEM_READ)
215 odata = d->modem_control;
216 else
217 d->modem_control = idata;
218 break;
219 case UART_LINE_STATUS: /* 0x1c */
220 odata = ULS_TE + ULS_TFE;
221 if (console_charavail(d->console_handle))
222 odata |= ULS_DR;
223 break;
224 case UART_CLOCK_DIVIDER: /* 0x28 */
225 break;
226 default:
227 if (writeflag == MEM_READ) {
228 debug("[ au1x00_uart%i: read from 0x%08lx ]\n",
229 d->uart_nr, (long)relative_addr);
230 } else {
231 debug("[ au1x00_uart%i: write to 0x%08lx: 0x%08llx"
232 " ]\n", d->uart_nr, (long)relative_addr,
233 (long long)idata);
234 }
235 }
236
237 if (writeflag == MEM_READ)
238 memory_writemax64(cpu, data, len, odata);
239
240 return 1;
241 }
242
243
244 /*
245 * dev_au1x00_pc_tick():
246 *
247 * Cause periodic ticks. (The PC is supposed to give interrupts at
248 * 32768 Hz?)
249 */
250 void dev_au1x00_pc_tick(struct cpu *cpu, void *extra)
251 {
252 struct au1x00_pc_data *d = extra;
253
254 if (d->reg[PC_COUNTER_CONTROL/4] & CC_EN1)
255 cpu_interrupt(cpu, 8 + d->irq_nr);
256 }
257
258
259 /*
260 * dev_au1x00_pc_access():
261 *
262 * Programmable Counters.
263 */
264 DEVICE_ACCESS(au1x00_pc)
265 {
266 struct au1x00_pc_data *d = extra;
267 uint64_t idata = 0, odata = 0;
268
269 if (writeflag == MEM_WRITE)
270 idata = memory_readmax64(cpu, data, len);
271
272 if (writeflag == MEM_READ)
273 odata = d->reg[relative_addr / sizeof(uint32_t)];
274 else
275 d->reg[relative_addr / sizeof(uint32_t)] = idata;
276
277 switch (relative_addr) {
278 default:
279 if (writeflag == MEM_READ) {
280 debug("[ au1x00_pc: read from 0x%08lx: 0x%08x ]\n",
281 (long)relative_addr, odata);
282 } else {
283 debug("[ au1x00_pc: write to 0x%08lx: 0x%08x ]\n",
284 (long)relative_addr, idata);
285 }
286 }
287
288 if (writeflag == MEM_READ)
289 memory_writemax64(cpu, data, len, odata);
290
291 return 1;
292 }
293
294
295 /*
296 * dev_au1x00_init():
297 */
298 struct au1x00_ic_data *dev_au1x00_init(struct machine *machine,
299 struct memory *mem)
300 {
301 struct au1x00_ic_data *d_ic0;
302 struct au1x00_ic_data *d_ic1;
303 struct au1x00_uart_data *d0;
304 struct au1x00_uart_data *d1;
305 struct au1x00_uart_data *d2;
306 struct au1x00_uart_data *d3;
307 struct au1x00_pc_data *d_pc;
308
309 d_ic0 = malloc(sizeof(struct au1x00_ic_data));
310 d_ic1 = malloc(sizeof(struct au1x00_ic_data));
311 d0 = malloc(sizeof(struct au1x00_uart_data));
312 d1 = malloc(sizeof(struct au1x00_uart_data));
313 d2 = malloc(sizeof(struct au1x00_uart_data));
314 d3 = malloc(sizeof(struct au1x00_uart_data));
315 d_pc = malloc(sizeof(struct au1x00_pc_data));
316
317 if (d0 == NULL || d1 == NULL || d2 == NULL ||
318 d3 == NULL || d_pc == NULL || d_ic0 == NULL
319 || d_ic1 == NULL) {
320 fprintf(stderr, "out of memory\n");
321 exit(1);
322 }
323 memset(d_ic0, 0, sizeof(struct au1x00_ic_data));
324 memset(d_ic1, 0, sizeof(struct au1x00_ic_data));
325 memset(d0, 0, sizeof(struct au1x00_uart_data));
326 memset(d1, 0, sizeof(struct au1x00_uart_data));
327 memset(d2, 0, sizeof(struct au1x00_uart_data));
328 memset(d3, 0, sizeof(struct au1x00_uart_data));
329 memset(d_pc, 0, sizeof(struct au1x00_pc_data));
330
331 d_ic0->ic_nr = 0;
332 d_ic1->ic_nr = 1;
333
334 d0->uart_nr = 0; d0->irq_nr = 0;
335 d1->uart_nr = 1; d1->irq_nr = 1;
336 d2->uart_nr = 2; d2->irq_nr = 2;
337 d3->uart_nr = 3; d3->irq_nr = 3;
338
339 /* Only allow input on the first UART, by default: */
340 d0->console_handle = console_start_slave(machine, "AU1x00 port 0", 1);
341 d1->console_handle = console_start_slave(machine, "AU1x00 port 1", 0);
342 d2->console_handle = console_start_slave(machine, "AU1x00 port 2", 0);
343 d3->console_handle = console_start_slave(machine, "AU1x00 port 3", 0);
344 d0->in_use = 1;
345 d1->in_use = 0;
346 d2->in_use = 0;
347 d3->in_use = 0;
348
349 d_pc->irq_nr = 14;
350
351 memory_device_register(mem, "au1x00_ic0",
352 IC0_BASE, 0x100, dev_au1x00_ic_access, d_ic0, DM_DEFAULT, NULL);
353 memory_device_register(mem, "au1x00_ic1",
354 IC1_BASE, 0x100, dev_au1x00_ic_access, d_ic1, DM_DEFAULT, NULL);
355
356 memory_device_register(mem, "au1x00_uart0", UART0_BASE, UART_SIZE,
357 dev_au1x00_uart_access, d0, DM_DEFAULT, NULL);
358 memory_device_register(mem, "au1x00_uart1", UART1_BASE, UART_SIZE,
359 dev_au1x00_uart_access, d1, DM_DEFAULT, NULL);
360 memory_device_register(mem, "au1x00_uart2", UART2_BASE, UART_SIZE,
361 dev_au1x00_uart_access, d2, DM_DEFAULT, NULL);
362 memory_device_register(mem, "au1x00_uart3", UART3_BASE, UART_SIZE,
363 dev_au1x00_uart_access, d3, DM_DEFAULT, NULL);
364
365 memory_device_register(mem, "au1x00_pc", PC_BASE, PC_SIZE + 0x8,
366 dev_au1x00_pc_access, d_pc, DM_DEFAULT, NULL);
367 machine_add_tickfunction(machine, dev_au1x00_pc_tick, d_pc, 15);
368
369 return d_ic0;
370 }
371

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