/[gxemul]/trunk/src/devices/dev_au1x00.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Diff of /trunk/src/devices/dev_au1x00.c

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revision 18 by dpavlin, Mon Oct 8 16:19:11 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2004-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2004-2006  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_au1x00.c,v 1.13 2005/10/26 14:37:03 debug Exp $   *  $Id: dev_au1x00.c,v 1.16 2006/01/01 13:17:16 debug Exp $
29   *     *  
30   *  Au1x00 (eg Au1500) pseudo device. See aureg.h for bitfield details.   *  Au1x00 (eg Au1500) pseudo device. See aureg.h for bitfield details.
31   *   *
# Line 52  struct au1x00_uart_data { Line 52  struct au1x00_uart_data {
52          int             console_handle;          int             console_handle;
53          int             uart_nr;          int             uart_nr;
54          int             irq_nr;          int             irq_nr;
55            int             in_use;
56          uint32_t        int_enable;          uint32_t        int_enable;
57          uint32_t        modem_control;          uint32_t        modem_control;
58  };  };
# Line 68  struct au1x00_pc_data { Line 69  struct au1x00_pc_data {
69   *   *
70   *  Interrupt Controller.   *  Interrupt Controller.
71   */   */
72  int dev_au1x00_ic_access(struct cpu *cpu, struct memory *mem,  DEVICE_ACCESS(au1x00_ic)
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
73  {  {
74          struct au1x00_ic_data *d = extra;          struct au1x00_ic_data *d = extra;
75          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
# Line 190  int dev_au1x00_ic_access(struct cpu *cpu Line 189  int dev_au1x00_ic_access(struct cpu *cpu
189   *   *
190   *  UART (Serial controllers).   *  UART (Serial controllers).
191   */   */
192  int dev_au1x00_uart_access(struct cpu *cpu, struct memory *mem,  DEVICE_ACCESS(au1x00_uart)
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
193  {  {
194          struct au1x00_uart_data *d = extra;          struct au1x00_uart_data *d = extra;
195          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
# Line 264  void dev_au1x00_pc_tick(struct cpu *cpu, Line 261  void dev_au1x00_pc_tick(struct cpu *cpu,
261   *   *
262   *  Programmable Counters.   *  Programmable Counters.
263   */   */
264  int dev_au1x00_pc_access(struct cpu *cpu, struct memory *mem,  DEVICE_ACCESS(au1x00_pc)
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
265  {  {
266          struct au1x00_pc_data *d = extra;          struct au1x00_pc_data *d = extra;
267          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
# Line 341  struct au1x00_ic_data *dev_au1x00_init(s Line 336  struct au1x00_ic_data *dev_au1x00_init(s
336          d2->uart_nr = 2; d2->irq_nr = 2;          d2->uart_nr = 2; d2->irq_nr = 2;
337          d3->uart_nr = 3; d3->irq_nr = 3;          d3->uart_nr = 3; d3->irq_nr = 3;
338    
339          d0->console_handle = console_start_slave(machine, "AU1x00 port 0");          /*  Only allow input on the first UART, by default:  */
340          d1->console_handle = console_start_slave(machine, "AU1x00 port 1");          d0->console_handle = console_start_slave(machine, "AU1x00 port 0", 1);
341          d2->console_handle = console_start_slave(machine, "AU1x00 port 2");          d1->console_handle = console_start_slave(machine, "AU1x00 port 1", 0);
342          d3->console_handle = console_start_slave(machine, "AU1x00 port 3");          d2->console_handle = console_start_slave(machine, "AU1x00 port 2", 0);
343            d3->console_handle = console_start_slave(machine, "AU1x00 port 3", 0);
344            d0->in_use = 1;
345            d1->in_use = 0;
346            d2->in_use = 0;
347            d3->in_use = 0;
348    
349          d_pc->irq_nr = 14;          d_pc->irq_nr = 14;
350    
351          memory_device_register(mem, "au1x00_ic0",          memory_device_register(mem, "au1x00_ic0",
352              IC0_BASE, 0x100, dev_au1x00_ic_access, d_ic0, MEM_DEFAULT, NULL);              IC0_BASE, 0x100, dev_au1x00_ic_access, d_ic0, DM_DEFAULT, NULL);
353          memory_device_register(mem, "au1x00_ic1",          memory_device_register(mem, "au1x00_ic1",
354              IC1_BASE, 0x100, dev_au1x00_ic_access, d_ic1, MEM_DEFAULT, NULL);              IC1_BASE, 0x100, dev_au1x00_ic_access, d_ic1, DM_DEFAULT, NULL);
355    
356          memory_device_register(mem, "au1x00_uart0", UART0_BASE, UART_SIZE,          memory_device_register(mem, "au1x00_uart0", UART0_BASE, UART_SIZE,
357              dev_au1x00_uart_access, d0, MEM_DEFAULT, NULL);              dev_au1x00_uart_access, d0, DM_DEFAULT, NULL);
358          memory_device_register(mem, "au1x00_uart1", UART1_BASE, UART_SIZE,          memory_device_register(mem, "au1x00_uart1", UART1_BASE, UART_SIZE,
359              dev_au1x00_uart_access, d1, MEM_DEFAULT, NULL);              dev_au1x00_uart_access, d1, DM_DEFAULT, NULL);
360          memory_device_register(mem, "au1x00_uart2", UART2_BASE, UART_SIZE,          memory_device_register(mem, "au1x00_uart2", UART2_BASE, UART_SIZE,
361              dev_au1x00_uart_access, d2, MEM_DEFAULT, NULL);              dev_au1x00_uart_access, d2, DM_DEFAULT, NULL);
362          memory_device_register(mem, "au1x00_uart3", UART3_BASE, UART_SIZE,          memory_device_register(mem, "au1x00_uart3", UART3_BASE, UART_SIZE,
363              dev_au1x00_uart_access, d3, MEM_DEFAULT, NULL);              dev_au1x00_uart_access, d3, DM_DEFAULT, NULL);
364    
365          memory_device_register(mem, "au1x00_pc", PC_BASE, PC_SIZE + 0x8,          memory_device_register(mem, "au1x00_pc", PC_BASE, PC_SIZE + 0x8,
366              dev_au1x00_pc_access, d_pc, MEM_DEFAULT, NULL);              dev_au1x00_pc_access, d_pc, DM_DEFAULT, NULL);
367          machine_add_tickfunction(machine, dev_au1x00_pc_tick, d_pc, 15);          machine_add_tickfunction(machine, dev_au1x00_pc_tick, d_pc, 15);
368    
369          return d_ic0;          return d_ic0;
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