/[gxemul]/trunk/src/devices/dev_au1x00.c
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revision 33 by dpavlin, Mon Oct 8 16:20:40 2007 UTC revision 34 by dpavlin, Mon Oct 8 16:21:17 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2004-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2004-2007  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_au1x00.c,v 1.18 2006/07/23 14:37:34 debug Exp $   *  $Id: dev_au1x00.c,v 1.22 2007/01/28 14:40:54 debug Exp $
29   *     *  
30   *  Au1x00 (eg Au1500) pseudo device. See aureg.h for bitfield details.   *  Au1x00 (eg Au1500) pseudo device. See aureg.h for bitfield details.
31   *   *
# Line 40  Line 40 
40    
41  #include "console.h"  #include "console.h"
42  #include "cpu.h"  #include "cpu.h"
43  #include "devices.h"  #include "device.h"
44  #include "machine.h"  #include "machine.h"
45  #include "memory.h"  #include "memory.h"
46  #include "misc.h"  #include "misc.h"
# Line 48  Line 48 
48  #include "aureg.h"  #include "aureg.h"
49    
50    
51    struct au1x00_ic_data {
52            int             ic_nr;
53            uint32_t        request0_int;
54            uint32_t        request1_int;
55            uint32_t        config0;
56            uint32_t        config1;
57            uint32_t        config2;
58            uint32_t        source;
59            uint32_t        assign_request;
60            uint32_t        wakeup;
61            uint32_t        mask;
62    };
63    
64  struct au1x00_uart_data {  struct au1x00_uart_data {
65          int             console_handle;          int             console_handle;
66          int             uart_nr;          int             uart_nr;
# Line 64  struct au1x00_pc_data { Line 77  struct au1x00_pc_data {
77  };  };
78    
79    
80    #if 0
81    /*  TODO: Convert this to the new interrupt syntax  */
82    /*
83     *  Au1x00 interrupt routine:
84     *
85     *  TODO: This is just bogus so far.  For more info, read this:
86     *  http://www.meshcube.org/cgi-bin/viewcvs.cgi/kernel/linux/arch/
87     *      mips/au1000/common/
88     *
89     *  CPU int 2 = IC 0, request 0
90     *  CPU int 3 = IC 0, request 1
91     *  CPU int 4 = IC 1, request 0
92     *  CPU int 5 = IC 1, request 1
93     *
94     *  Interrupts 0..31 are on interrupt controller 0, interrupts 32..63 are
95     *  on controller 1.
96     *
97     *  Special case: if irq_nr == 64+8, then this just updates the CPU
98     *  interrupt assertions.
99     */
100    void au1x00_interrupt(struct machine *m, struct cpu *cpu,
101            int irq_nr, int assrt)
102    {
103            uint32_t ms;
104    
105            irq_nr -= 8;
106            debug("au1x00_interrupt(): irq_nr=%i assrt=%i\n", irq_nr, assrt);
107    
108            if (irq_nr < 64) {
109                    ms = 1 << (irq_nr & 31);
110    
111    fatal("TODO: legacy interrupt rewrite!\n");
112    abort();
113    
114    //              if (assrt)
115    //                      m->md_int.au1x00_ic_data->request0_int |= ms;
116    //              else
117    //                      m->md_int.au1x00_ic_data->request0_int &= ~ms;
118    
119                    /*  TODO: Controller 1  */
120            }
121    
122    fatal("TODO: legacy interrupt rewrite!\n");
123    abort();
124    
125    //      if ((m->md_int.au1x00_ic_data->request0_int &
126    //          m->md_int.au1x00_ic_data->mask) != 0)
127    //              cpu_interrupt(cpu, 2);
128    //      else
129    //              cpu_interrupt_ack(cpu, 2);
130    
131            /*  TODO: What _is_ request1?  */
132    
133            /*  TODO: Controller 1  */
134    }
135    #endif
136    
137    
138  /*  /*
139   *  dev_au1x00_ic_access():   *  dev_au1x00_ic_access():
140   *   *
# Line 174  DEVICE_ACCESS(au1x00_ic) Line 245  DEVICE_ACCESS(au1x00_ic)
245                  }                  }
246          }          }
247    
248          if (writeflag == MEM_WRITE)  fatal("TODO: legacy interrupt rewrite!\n");
249                  cpu_interrupt(cpu, 8 + 64);  abort();
250    
251    //      if (writeflag == MEM_WRITE)
252    //              cpu_interrupt(cpu, 8 + 64);
253    
254          if (writeflag == MEM_READ)          if (writeflag == MEM_READ)
255                  memory_writemax64(cpu, data, len, odata);                  memory_writemax64(cpu, data, len, odata);
# Line 243  DEVICE_ACCESS(au1x00_uart) Line 317  DEVICE_ACCESS(au1x00_uart)
317    
318  DEVICE_TICK(au1x00_pc)  DEVICE_TICK(au1x00_pc)
319  {  {
320          struct au1x00_pc_data *d = extra;  /*      struct au1x00_pc_data *d = extra;  */
321    
322          /*  Periodic ticks at 32768 Hz? TODO  */          /*  Periodic ticks at 32768 Hz? TODO  */
323    
324          if (d->reg[PC_COUNTER_CONTROL/4] & CC_EN1)  fatal("TODO: legacy interrupt rewrite!\n");
325                  cpu_interrupt(cpu, 8 + d->irq_nr);  abort();
326    
327    //      if (d->reg[PC_COUNTER_CONTROL/4] & CC_EN1)
328    //              cpu_interrupt(cpu, 8 + d->irq_nr);
329  }  }
330    
331    
# Line 288  DEVICE_ACCESS(au1x00_pc) Line 365  DEVICE_ACCESS(au1x00_pc)
365  }  }
366    
367    
368  /*  DEVINIT(au1x00)
  *  dev_au1x00_init():  
  */  
 struct au1x00_ic_data *dev_au1x00_init(struct machine *machine,  
         struct memory *mem)  
369  {  {
370            struct machine *machine = devinit->machine;
371          struct au1x00_ic_data *d_ic0;          struct au1x00_ic_data *d_ic0;
372          struct au1x00_ic_data *d_ic1;          struct au1x00_ic_data *d_ic1;
373          struct au1x00_uart_data *d0;          struct au1x00_uart_data *d0;
# Line 344  struct au1x00_ic_data *dev_au1x00_init(s Line 418  struct au1x00_ic_data *dev_au1x00_init(s
418    
419          d_pc->irq_nr = 14;          d_pc->irq_nr = 14;
420    
421          memory_device_register(mem, "au1x00_ic0",          memory_device_register(machine->memory, "au1x00_ic0",
422              IC0_BASE, 0x100, dev_au1x00_ic_access, d_ic0, DM_DEFAULT, NULL);              IC0_BASE, 0x100, dev_au1x00_ic_access, d_ic0, DM_DEFAULT, NULL);
423          memory_device_register(mem, "au1x00_ic1",          memory_device_register(machine->memory, "au1x00_ic1",
424              IC1_BASE, 0x100, dev_au1x00_ic_access, d_ic1, DM_DEFAULT, NULL);              IC1_BASE, 0x100, dev_au1x00_ic_access, d_ic1, DM_DEFAULT, NULL);
425    
426          memory_device_register(mem, "au1x00_uart0", UART0_BASE, UART_SIZE,          memory_device_register(machine->memory, "au1x00_uart0", UART0_BASE,
427              dev_au1x00_uart_access, d0, DM_DEFAULT, NULL);              UART_SIZE, dev_au1x00_uart_access, d0, DM_DEFAULT, NULL);
428          memory_device_register(mem, "au1x00_uart1", UART1_BASE, UART_SIZE,          memory_device_register(machine->memory, "au1x00_uart1", UART1_BASE,
429              dev_au1x00_uart_access, d1, DM_DEFAULT, NULL);              UART_SIZE, dev_au1x00_uart_access, d1, DM_DEFAULT, NULL);
430          memory_device_register(mem, "au1x00_uart2", UART2_BASE, UART_SIZE,          memory_device_register(machine->memory, "au1x00_uart2", UART2_BASE,
431              dev_au1x00_uart_access, d2, DM_DEFAULT, NULL);              UART_SIZE, dev_au1x00_uart_access, d2, DM_DEFAULT, NULL);
432          memory_device_register(mem, "au1x00_uart3", UART3_BASE, UART_SIZE,          memory_device_register(machine->memory, "au1x00_uart3", UART3_BASE,
433              dev_au1x00_uart_access, d3, DM_DEFAULT, NULL);              UART_SIZE, dev_au1x00_uart_access, d3, DM_DEFAULT, NULL);
434    
435          memory_device_register(mem, "au1x00_pc", PC_BASE, PC_SIZE + 0x8,          memory_device_register(machine->memory, "au1x00_pc", PC_BASE,
436              dev_au1x00_pc_access, d_pc, DM_DEFAULT, NULL);              PC_SIZE+0x8, dev_au1x00_pc_access, d_pc, DM_DEFAULT, NULL);
437          machine_add_tickfunction(machine, dev_au1x00_pc_tick, d_pc, 15, 0.0);          machine_add_tickfunction(machine, dev_au1x00_pc_tick, d_pc, 15, 0.0);
438    
439          return d_ic0;          return 1;
440  }  }
441    
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