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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_asc.c,v 1.86 2007/06/15 18:44:19 debug Exp $ |
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* |
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* COMMENT: NCR53C9X "ASC" SCSI controller |
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* |
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* This is the SCSI controller used in some DECstation/DECsystem models and |
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* the PICA-61 machine. |
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* |
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* Supposed to support SCSI-1 and SCSI-2. I've not yet found any docs |
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* on NCR53C9X, so I'll try to implement this device from LSI53CF92A docs |
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* instead. |
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* |
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* |
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* Memory layout on DECstation: |
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* |
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* NCR53C94 registers at base + 0 |
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* DMA address register at base + 0x40000 |
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* 128K SRAM buffer at base + 0x80000 |
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* ROM at base + 0xc0000 |
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* |
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* Memory layout on PICA-61: |
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* |
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* I haven't had time to look this up yet, but length = 0x1000. |
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* |
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* |
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* TODO: This module needs a clean-up, and some testing to see that |
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* it works will all OSes that might use it (NetBSD, OpenBSD, |
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* Ultrix, Linux, Mach, OSF/1, Sprite, ...) |
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* |
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* Running Linux/DECstation 2.4.26 with no scsi disks attached causes |
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* a warning message to be printed by Linux. (Whether this is a bug, |
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* is is the way it works on real hardware, I don't know.) |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "devices.h" |
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#include "diskimage.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "ncr53c9xreg.h" |
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|
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|
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/* #define ASC_DEBUG */ |
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/* #define debug fatal */ |
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/* #define ASC_FULL_REGISTER_ACCESS_DEBUG */ |
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/* static int quiet_mode = 0; */ |
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|
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#define ASC_TICK_SHIFT 15 |
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|
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extern int quiet_mode; |
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|
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|
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#define ASC_FIFO_LEN 16 |
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#define STATE_DISCONNECTED 0 |
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#define STATE_INITIATOR 1 |
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#define STATE_TARGET 2 |
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|
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#define PHASE_DATA_OUT 0 |
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#define PHASE_DATA_IN 1 |
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#define PHASE_COMMAND 2 |
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#define PHASE_STATUS 3 |
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#define PHASE_MSG_OUT 6 |
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#define PHASE_MSG_IN 7 |
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|
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|
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/* The controller's SCSI id: */ |
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#define ASC_SCSI_ID 7 |
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|
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#define ASC_DMA_SIZE (128*1024) |
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|
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struct asc_data { |
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int mode; |
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|
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void *turbochannel; |
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struct interrupt irq; |
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int irq_asserted; |
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|
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/* Current state and transfer: */ |
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int cur_state; |
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int cur_phase; |
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struct scsi_transfer *xferp; |
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|
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/* FIFO: */ |
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unsigned char fifo[ASC_FIFO_LEN]; |
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int fifo_in; |
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int fifo_out; |
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int n_bytes_in_fifo; /* cached */ |
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|
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/* ATN signal: */ |
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int atn; |
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|
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/* Incoming dma data: */ |
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unsigned char *incoming_data; |
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int incoming_len; |
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int incoming_data_addr; |
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|
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/* Built-in DMA memory (for DECstation 5000/200): */ |
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uint32_t dma_address_reg; |
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unsigned char *dma_address_reg_memory; |
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unsigned char *dma; |
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|
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void *dma_controller_data; |
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size_t (*dma_controller)(void *dma_controller_data, |
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unsigned char *data, size_t len, int writeflag); |
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|
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/* Read registers and write registers: */ |
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uint32_t reg_ro[0x10]; |
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uint32_t reg_wo[0x10]; |
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}; |
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|
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/* (READ/WRITE name, if split) */ |
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char *asc_reg_names[0x10] = { |
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"NCR_TCL", "NCR_TCM", "NCR_FIFO", "NCR_CMD", |
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"NCR_STAT/NCR_SELID", "NCR_INTR/NCR_TIMEOUT", |
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"NCR_STEP/NCR_SYNCTP", "NCR_FFLAG/NCR_SYNCOFF", |
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"NCR_CFG1", "NCR_CCF", "NCR_TEST", "NCR_CFG2", |
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"NCR_CFG3", "reg_0xd", "NCR_TCH", "reg_0xf" |
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}; |
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|
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|
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/* This is referenced below. */ |
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static int dev_asc_select(struct cpu *cpu, struct asc_data *d, int from_id, |
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int to_id, int dmaflag, int n_messagebytes); |
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|
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|
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DEVICE_TICK(asc) |
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{ |
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struct asc_data *d = extra; |
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int new_assert = d->reg_ro[NCR_STAT] & NCRSTAT_INT; |
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|
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if (new_assert && !d->irq_asserted) |
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INTERRUPT_ASSERT(d->irq); |
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|
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d->irq_asserted = new_assert; |
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} |
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|
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|
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/* |
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* dev_asc_fifo_flush(): |
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* |
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* Flush the fifo. |
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*/ |
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static void dev_asc_fifo_flush(struct asc_data *d) |
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{ |
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d->fifo[0] = 0x00; |
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d->fifo_in = 0; |
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d->fifo_out = 0; |
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d->n_bytes_in_fifo = 0; |
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} |
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|
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|
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/* |
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* dev_asc_reset(): |
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* |
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* Reset the state of the asc. |
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*/ |
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static void dev_asc_reset(struct asc_data *d) |
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{ |
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d->cur_state = STATE_DISCONNECTED; |
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d->atn = 0; |
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|
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if (d->xferp != NULL) |
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scsi_transfer_free(d->xferp); |
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d->xferp = NULL; |
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|
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dev_asc_fifo_flush(d); |
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|
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/* According to table 4.1 in the LSI53CF92A manual: */ |
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memset(d->reg_wo, 0, sizeof(d->reg_wo)); |
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d->reg_wo[NCR_TCH] = 0x94; |
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d->reg_wo[NCR_CCF] = 2; |
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memcpy(d->reg_ro, d->reg_wo, sizeof(d->reg_ro)); |
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d->reg_wo[NCR_SYNCTP] = 5; |
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} |
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|
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|
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/* |
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* dev_asc_fifo_read(): |
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* |
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* Read a byte from the asc FIFO. |
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*/ |
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static int dev_asc_fifo_read(struct asc_data *d) |
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{ |
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int res = d->fifo[d->fifo_out]; |
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|
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if (d->fifo_in == d->fifo_out) |
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fatal("dev_asc: WARNING! FIFO overrun!\n"); |
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|
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d->fifo_out = (d->fifo_out + 1) % ASC_FIFO_LEN; |
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d->n_bytes_in_fifo --; |
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|
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return res; |
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} |
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|
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|
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/* |
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* dev_asc_fifo_write(): |
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* |
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* Write a byte to the asc FIFO. |
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*/ |
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static void dev_asc_fifo_write(struct asc_data *d, unsigned char data) |
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{ |
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d->fifo[d->fifo_in] = data; |
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d->fifo_in = (d->fifo_in + 1) % ASC_FIFO_LEN; |
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d->n_bytes_in_fifo ++; |
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|
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if (d->fifo_in == d->fifo_out) |
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fatal("dev_asc: WARNING! FIFO overrun on write!\n"); |
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} |
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|
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|
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/* |
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* dev_asc_newxfer(): |
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* |
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* Allocate memory for a new transfer. |
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*/ |
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static void dev_asc_newxfer(struct asc_data *d) |
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{ |
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if (d->xferp != NULL) { |
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printf("WARNING! dev_asc_newxfer(): freeing previous" |
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" transfer\n"); |
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scsi_transfer_free(d->xferp); |
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d->xferp = NULL; |
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} |
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|
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d->xferp = scsi_transfer_alloc(); |
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#if 0 |
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d->xferp->get_data_out = dev_asc_get_data_out; |
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d->xferp->gdo_extra = (void *) d; |
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#endif |
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} |
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|
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|
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/* |
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* dev_asc_transfer(): |
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* |
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* Transfer data from a SCSI device to the controller (or vice versa), |
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* depending on the current phase. |
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* |
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* Returns 1 if ok, 0 on error. |
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*/ |
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static int dev_asc_transfer(struct cpu *cpu, struct asc_data *d, int dmaflag) |
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{ |
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int res = 1, all_done = 1; |
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int len, i, ch; |
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|
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if (!quiet_mode) |
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debug(" { TRANSFER to/from id %i: ", d->reg_wo[NCR_SELID] & 7); |
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|
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if (d->cur_phase == PHASE_DATA_IN) { |
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/* Data coming into the controller from external device: */ |
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if (!dmaflag) { |
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if (d->xferp->data_in == NULL) { |
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fatal("no incoming data?\n"); |
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res = 0; |
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} else { |
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/* TODO */ |
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fatal("TODO..............\n"); |
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len = d->reg_wo[NCR_TCL] + |
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d->reg_wo[NCR_TCM] * 256; |
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|
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len--; |
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ch = d->incoming_data[d->incoming_data_addr]; |
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debug(" %02x", ch); |
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|
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d->incoming_data_addr ++; |
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dev_asc_fifo_write(d, ch); |
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|
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if (len == 0) { |
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free(d->incoming_data); |
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d->incoming_data = NULL; |
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} |
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|
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d->reg_ro[NCR_TCL] = len & 255; |
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d->reg_ro[NCR_TCM] = (len >> 8) & 255; |
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} |
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} else { |
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/* Copy from the incoming data into dma memory: */ |
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if (d->xferp->data_in == NULL) { |
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fatal("no incoming DMA data?\n"); |
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res = 0; |
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} else { |
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size_t len = d->xferp->data_in_len; |
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size_t len2 = d->reg_wo[NCR_TCL] + |
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d->reg_wo[NCR_TCM] * 256; |
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if (len2 == 0) |
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len2 = 65536; |
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|
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if (len < len2) { |
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fatal("{ asc: data in, len=%i len2=%i " |
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"}\n", len, len2); |
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} |
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|
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/* TODO: check len2 in a similar way? */ |
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if (len + (d->dma_address_reg & |
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(ASC_DMA_SIZE-1)) > ASC_DMA_SIZE) |
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len = ASC_DMA_SIZE - |
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(d->dma_address_reg & |
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(ASC_DMA_SIZE-1)); |
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|
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if (len2 > len) { |
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memset(d->dma + (d->dma_address_reg & |
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(ASC_DMA_SIZE-1)), 0, len2); |
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len2 = len; |
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} |
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|
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#ifdef ASC_DEBUG |
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if (!quiet_mode) { |
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int i; |
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for (i=0; i<len; i++) |
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debug(" %02x", d->xferp-> |
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data_in[i]); |
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} |
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#endif |
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|
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/* |
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* Are we using an external DMA controller? |
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* Then use it. Otherwise place the data in |
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* the DECstation 5000/200 built-in DMA |
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* region. |
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*/ |
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if (d->dma_controller != NULL) |
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d->dma_controller( |
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d->dma_controller_data, |
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d->xferp->data_in, |
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len2, 1); |
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else |
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memcpy(d->dma + (d->dma_address_reg & |
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(ASC_DMA_SIZE-1)), |
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d->xferp->data_in, len2); |
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|
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if (d->xferp->data_in_len > len2) { |
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unsigned char *n; |
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|
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if (d->dma_controller != NULL) |
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printf("WARNING!!!!!!!!! BUG!!!! Unexpected stuff..." |
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"len2=%i d->xferp->data_in_len=%i\n", (int)len2, |
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(int)d->xferp->data_in_len); |
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|
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all_done = 0; |
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/* fatal("{ asc: multi-transfer" |
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" data_in, len=%i len2=%i }\n", |
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(int)len, (int)len2); */ |
376 |
|
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d->xferp->data_in_len -= len2; |
378 |
CHECK_ALLOCATION(n = |
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malloc(d->xferp->data_in_len)); |
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memcpy(n, d->xferp->data_in + len2, |
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d->xferp->data_in_len); |
382 |
free(d->xferp->data_in); |
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d->xferp->data_in = n; |
384 |
|
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len = len2; |
386 |
} |
387 |
|
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len = 0; |
389 |
|
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d->reg_ro[NCR_TCL] = len & 255; |
391 |
d->reg_ro[NCR_TCM] = (len >> 8) & 255; |
392 |
|
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/* Successful DMA transfer: */ |
394 |
d->reg_ro[NCR_STAT] |= NCRSTAT_TC; |
395 |
} |
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} |
397 |
} else if (d->cur_phase == PHASE_DATA_OUT) { |
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/* Data going from the controller to an external device: */ |
399 |
if (!dmaflag) { |
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fatal("TODO.......asdgasin\n"); |
401 |
} else { |
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/* Copy data from DMA to data_out: */ |
403 |
int len = d->xferp->data_out_len; |
404 |
int len2 = d->reg_wo[NCR_TCL] + |
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d->reg_wo[NCR_TCM] * 256; |
406 |
if (len2 == 0) |
407 |
len2 = 65536; |
408 |
|
409 |
if (len == 0) { |
410 |
fprintf(stderr, "d->xferp->data_out_len == " |
411 |
"0 ?\n"); |
412 |
exit(1); |
413 |
} |
414 |
|
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/* TODO: Make sure that len2 doesn't go outside |
416 |
of the dma memory? */ |
417 |
|
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/* fatal(" data out offset=%5i len=%5i\n", |
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d->xferp->data_out_offset, len2); */ |
420 |
|
421 |
if (d->xferp->data_out_offset + len2 > |
422 |
d->xferp->data_out_len) { |
423 |
len2 = d->xferp->data_out_len - |
424 |
d->xferp->data_out_offset; |
425 |
} |
426 |
|
427 |
/* |
428 |
* Are we using an external DMA controller? Then use |
429 |
* it. Otherwise place the data in the DECstation |
430 |
* 5000/200 built-in DMA region. |
431 |
*/ |
432 |
if (d->xferp->data_out == NULL) { |
433 |
scsi_transfer_allocbuf(&d->xferp->data_out_len, |
434 |
&d->xferp->data_out, len, 0); |
435 |
|
436 |
if (d->dma_controller != NULL) |
437 |
d->dma_controller( |
438 |
d->dma_controller_data, |
439 |
d->xferp->data_out, |
440 |
len2, 0); |
441 |
else |
442 |
memcpy(d->xferp->data_out, |
443 |
d->dma + (d->dma_address_reg & |
444 |
(ASC_DMA_SIZE-1)), len2); |
445 |
d->xferp->data_out_offset = len2; |
446 |
} else { |
447 |
/* Continuing a multi-transfer: */ |
448 |
if (d->dma_controller != NULL) |
449 |
d->dma_controller( |
450 |
d->dma_controller_data, |
451 |
d->xferp->data_out + |
452 |
d->xferp->data_out_offset, |
453 |
len2, 0); |
454 |
else |
455 |
memcpy(d->xferp->data_out + |
456 |
d->xferp->data_out_offset, |
457 |
d->dma + (d->dma_address_reg & |
458 |
(ASC_DMA_SIZE-1)), len2); |
459 |
d->xferp->data_out_offset += len2; |
460 |
} |
461 |
|
462 |
/* If the disk wants more than we're DMAing, |
463 |
then this is a multitransfer: */ |
464 |
if (d->xferp->data_out_offset != |
465 |
d->xferp->data_out_len) { |
466 |
if (!quiet_mode) |
467 |
debug("[ asc: data_out, multitransfer " |
468 |
"len = %i, len2 = %i ]\n", |
469 |
(int)len, (int)len2); |
470 |
if (d->xferp->data_out_offset > |
471 |
d->xferp->data_out_len) |
472 |
fatal("[ asc data_out dma: too much?" |
473 |
" ]\n"); |
474 |
else |
475 |
all_done = 0; |
476 |
} |
477 |
|
478 |
#ifdef ASC_DEBUG |
479 |
if (!quiet_mode) { |
480 |
int i; |
481 |
for (i=0; i<len; i++) |
482 |
debug(" %02x", d->xferp->data_out[i]); |
483 |
} |
484 |
#endif |
485 |
len = 0; |
486 |
|
487 |
d->reg_ro[NCR_TCL] = len & 255; |
488 |
d->reg_ro[NCR_TCM] = (len >> 8) & 255; |
489 |
|
490 |
/* Successful DMA transfer: */ |
491 |
d->reg_ro[NCR_STAT] |= NCRSTAT_TC; |
492 |
} |
493 |
} else if (d->cur_phase == PHASE_MSG_OUT) { |
494 |
if (!quiet_mode) |
495 |
debug("MSG OUT: "); |
496 |
/* Data going from the controller to an external device: */ |
497 |
if (!dmaflag) { |
498 |
/* There should already be one byte in msg_out, so we |
499 |
just extend the message: */ |
500 |
int oldlen = d->xferp->msg_out_len; |
501 |
int newlen; |
502 |
|
503 |
if (oldlen != 1) { |
504 |
fatal(" (PHASE OUT MSG len == %i, " |
505 |
"should be 1)\n", oldlen); |
506 |
} |
507 |
|
508 |
newlen = oldlen + d->n_bytes_in_fifo; |
509 |
CHECK_ALLOCATION(d->xferp->msg_out = |
510 |
realloc(d->xferp->msg_out, newlen)); |
511 |
d->xferp->msg_out_len = newlen; |
512 |
|
513 |
i = oldlen; |
514 |
while (d->fifo_in != d->fifo_out) { |
515 |
ch = dev_asc_fifo_read(d); |
516 |
d->xferp->msg_out[i++] = ch; |
517 |
#ifdef ASC_DEBUG |
518 |
debug("0x%02x ", ch); |
519 |
#endif |
520 |
} |
521 |
|
522 |
#ifdef MACH |
523 |
/* Super-ugly hack for Mach/PMAX: TODO: make nicer */ |
524 |
if (d->xferp->msg_out_len == 6 && |
525 |
(d->xferp->msg_out[0] == 0x80 || |
526 |
d->xferp->msg_out[0] == 0xc0) && |
527 |
d->xferp->msg_out[1] == 0x01 && |
528 |
d->xferp->msg_out[2] == 0x03 && |
529 |
d->xferp->msg_out[3] == 0x01 && |
530 |
d->xferp->msg_out[4] == 0x32 && |
531 |
d->xferp->msg_out[5] == 0x0f) { |
532 |
fatal(" !! Mach/PMAX hack !! "); |
533 |
all_done = 0; |
534 |
d->cur_phase = PHASE_MSG_IN; |
535 |
} |
536 |
#endif |
537 |
} else { |
538 |
/* Copy data from DMA to msg_out: */ |
539 |
fatal("[ DMA MSG OUT: xxx TODO! ]"); |
540 |
/* TODO */ |
541 |
res = 0; |
542 |
} |
543 |
} else if (d->cur_phase == PHASE_MSG_IN) { |
544 |
if (!quiet_mode) |
545 |
debug(" MSG IN"); |
546 |
fatal("[ MACH HACK! ]"); |
547 |
/* Super-ugly hack for Mach/PMAX: TODO: make nicer */ |
548 |
dev_asc_fifo_write(d, 0x07); |
549 |
d->cur_phase = PHASE_COMMAND; |
550 |
all_done = 0; |
551 |
} else if (d->cur_phase == PHASE_COMMAND) { |
552 |
if (!quiet_mode) |
553 |
debug(" COMMAND ==> select "); |
554 |
res = dev_asc_select(cpu, d, d->reg_ro[NCR_CFG1] & 7, |
555 |
d->reg_wo[NCR_SELID] & 7, dmaflag, 0); |
556 |
return res; |
557 |
} else { |
558 |
fatal("!!! TODO: unknown/unimplemented phase " |
559 |
"in transfer: %i\n", d->cur_phase); |
560 |
} |
561 |
|
562 |
/* Redo the command if data was just sent using DATA_OUT: */ |
563 |
if (d->cur_phase == PHASE_DATA_OUT) { |
564 |
res = diskimage_scsicommand(cpu, d->reg_wo[NCR_SELID] & 7, |
565 |
DISKIMAGE_SCSI, d->xferp); |
566 |
} |
567 |
|
568 |
if (all_done) { |
569 |
if (d->cur_phase == PHASE_MSG_OUT) |
570 |
d->cur_phase = PHASE_COMMAND; |
571 |
else |
572 |
d->cur_phase = PHASE_STATUS; |
573 |
} |
574 |
|
575 |
/* |
576 |
* Cause an interrupt after the transfer: |
577 |
* |
578 |
* NOTE: Earlier I had this in here as well: |
579 |
* d->reg_ro[NCR_INTR] |= NCRINTR_FC; |
580 |
* but Linux/DECstation and OpenBSD/pmax seems to choke on that. |
581 |
*/ |
582 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
583 |
d->reg_ro[NCR_INTR] |= NCRINTR_BS; |
584 |
d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | d->cur_phase; |
585 |
d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 4; /* 4? */ |
586 |
|
587 |
if (!quiet_mode) |
588 |
debug("}"); |
589 |
return res; |
590 |
} |
591 |
|
592 |
|
593 |
/* |
594 |
* dev_asc_select(): |
595 |
* |
596 |
* Select a SCSI device, send msg bytes (if any), and send command bytes. |
597 |
* (Call diskimage_scsicommand() to handle the command.) |
598 |
* |
599 |
* Return value: 1 if ok, 0 on error. |
600 |
*/ |
601 |
static int dev_asc_select(struct cpu *cpu, struct asc_data *d, int from_id, |
602 |
int to_id, int dmaflag, int n_messagebytes) |
603 |
{ |
604 |
int ok, len, i, ch; |
605 |
|
606 |
if (!quiet_mode) |
607 |
debug(" { SELECT id %i: ", to_id); |
608 |
|
609 |
/* |
610 |
* Message bytes, if any: |
611 |
*/ |
612 |
if (!quiet_mode) |
613 |
debug("msg:"); |
614 |
|
615 |
if (n_messagebytes > 0) { |
616 |
scsi_transfer_allocbuf(&d->xferp->msg_out_len, |
617 |
&d->xferp->msg_out, n_messagebytes, 0); |
618 |
|
619 |
i = 0; |
620 |
while (n_messagebytes-- > 0) { |
621 |
int ch = dev_asc_fifo_read(d); |
622 |
if (!quiet_mode) |
623 |
debug(" %02x", ch); |
624 |
d->xferp->msg_out[i++] = ch; |
625 |
} |
626 |
|
627 |
if ((d->xferp->msg_out[0] & 0x7) != 0x00) { |
628 |
debug(" (LUNs not implemented yet: 0x%02x) }", |
629 |
d->xferp->msg_out[0]); |
630 |
return 0; |
631 |
} |
632 |
|
633 |
if (((d->xferp->msg_out[0] & ~0x7) != 0xc0) && |
634 |
((d->xferp->msg_out[0] & ~0x7) != 0x80)) { |
635 |
fatal(" (Unimplemented msg out: 0x%02x) }", |
636 |
d->xferp->msg_out[0]); |
637 |
return 0; |
638 |
} |
639 |
|
640 |
if (d->xferp->msg_out_len > 1) { |
641 |
fatal(" (Long msg out, not implemented yet;" |
642 |
" len=%i) }", d->xferp->msg_out_len); |
643 |
return 0; |
644 |
} |
645 |
} else { |
646 |
if (!quiet_mode) |
647 |
debug(" none"); |
648 |
} |
649 |
|
650 |
/* Special case: SELATNS (with STOP sequence): */ |
651 |
if (d->cur_phase == PHASE_MSG_OUT) { |
652 |
if (!quiet_mode) |
653 |
debug(" MSG OUT DEBUG"); |
654 |
if (d->xferp->msg_out_len != 1) { |
655 |
fatal(" (SELATNS: msg out len == %i, should be 1)", |
656 |
d->xferp->msg_out_len); |
657 |
return 0; |
658 |
} |
659 |
|
660 |
/* d->cur_phase = PHASE_COMMAND; */ |
661 |
|
662 |
/* According to the LSI manual: */ |
663 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
664 |
d->reg_ro[NCR_INTR] |= NCRINTR_FC; |
665 |
d->reg_ro[NCR_INTR] |= NCRINTR_BS; |
666 |
d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | d->cur_phase; |
667 |
d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 1; |
668 |
|
669 |
if (!quiet_mode) |
670 |
debug("}"); |
671 |
return 1; |
672 |
} |
673 |
|
674 |
/* |
675 |
* Command bytes: |
676 |
*/ |
677 |
if (!quiet_mode) |
678 |
debug(", cmd: "); |
679 |
|
680 |
if (!dmaflag) { |
681 |
if (!quiet_mode) |
682 |
debug("[non-DMA] "); |
683 |
|
684 |
scsi_transfer_allocbuf(&d->xferp->cmd_len, |
685 |
&d->xferp->cmd, d->n_bytes_in_fifo, 0); |
686 |
|
687 |
i = 0; |
688 |
while (d->fifo_in != d->fifo_out) { |
689 |
ch = dev_asc_fifo_read(d); |
690 |
d->xferp->cmd[i++] = ch; |
691 |
if (!quiet_mode) |
692 |
debug("%02x ", ch); |
693 |
} |
694 |
} else { |
695 |
if (!quiet_mode) |
696 |
debug("[DMA] "); |
697 |
len = d->reg_wo[NCR_TCL] + d->reg_wo[NCR_TCM] * 256; |
698 |
if (len == 0) |
699 |
len = 65536; |
700 |
|
701 |
scsi_transfer_allocbuf(&d->xferp->cmd_len, |
702 |
&d->xferp->cmd, len, 0); |
703 |
|
704 |
for (i=0; i<len; i++) { |
705 |
int ofs = d->dma_address_reg + i; |
706 |
ch = d->dma[ofs & (ASC_DMA_SIZE-1)]; |
707 |
d->xferp->cmd[i] = ch; |
708 |
if (!quiet_mode) |
709 |
debug("%02x ", ch); |
710 |
} |
711 |
|
712 |
d->reg_ro[NCR_TCL] = len & 255; |
713 |
d->reg_ro[NCR_TCM] = (len >> 8) & 255; |
714 |
|
715 |
d->reg_ro[NCR_STAT] |= NCRSTAT_TC; |
716 |
} |
717 |
|
718 |
/* |
719 |
* Call the SCSI device to perform the command: |
720 |
*/ |
721 |
ok = diskimage_scsicommand(cpu, to_id, DISKIMAGE_SCSI, d->xferp); |
722 |
|
723 |
|
724 |
/* Cause an interrupt: */ |
725 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
726 |
d->reg_ro[NCR_INTR] |= NCRINTR_FC; |
727 |
d->reg_ro[NCR_INTR] |= NCRINTR_BS; |
728 |
|
729 |
if (ok == 2) |
730 |
d->cur_phase = PHASE_DATA_OUT; |
731 |
else if (d->xferp->data_in != NULL) |
732 |
d->cur_phase = PHASE_DATA_IN; |
733 |
else |
734 |
d->cur_phase = PHASE_STATUS; |
735 |
|
736 |
d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | d->cur_phase; |
737 |
d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 4; /* DONE (?) */ |
738 |
|
739 |
if (!quiet_mode) |
740 |
debug("}"); |
741 |
|
742 |
return ok; |
743 |
} |
744 |
|
745 |
|
746 |
DEVICE_ACCESS(asc_address_reg) |
747 |
{ |
748 |
struct asc_data *d = extra; |
749 |
|
750 |
if (relative_addr + len > 4) |
751 |
return 0; |
752 |
|
753 |
if (writeflag==MEM_READ) { |
754 |
memcpy(data, d->dma_address_reg_memory + relative_addr, len); |
755 |
} else { |
756 |
memcpy(d->dma_address_reg_memory + relative_addr, data, len); |
757 |
} |
758 |
|
759 |
return 1; |
760 |
} |
761 |
|
762 |
|
763 |
DEVICE_ACCESS(asc_dma) |
764 |
{ |
765 |
struct asc_data *d = extra; |
766 |
|
767 |
if (writeflag==MEM_READ) { |
768 |
memcpy(data, d->dma + relative_addr, len); |
769 |
#ifdef ASC_DEBUG |
770 |
{ |
771 |
int i; |
772 |
debug("[ asc: read from DMA addr 0x%05x:", |
773 |
(int) relative_addr); |
774 |
for (i=0; i<len; i++) |
775 |
debug(" %02x", data[i]); |
776 |
debug(" ]\n"); |
777 |
} |
778 |
#endif |
779 |
|
780 |
/* Don't return the common way, as that |
781 |
would overwrite data. */ |
782 |
return 1; |
783 |
} else { |
784 |
memcpy(d->dma + relative_addr, data, len); |
785 |
#ifdef ASC_DEBUG |
786 |
{ |
787 |
int i; |
788 |
debug("[ asc: write to DMA addr 0x%05x:", |
789 |
(int) relative_addr); |
790 |
for (i=0; i<len; i++) |
791 |
debug(" %02x", data[i]); |
792 |
debug(" ]\n"); |
793 |
} |
794 |
#endif |
795 |
/* Quick return. */ |
796 |
return 1; |
797 |
} |
798 |
} |
799 |
|
800 |
|
801 |
DEVICE_ACCESS(asc) |
802 |
{ |
803 |
int regnr; |
804 |
struct asc_data *d = extra; |
805 |
int target_exists; |
806 |
int n_messagebytes = 0; |
807 |
uint64_t idata = 0, odata = 0; |
808 |
|
809 |
if (writeflag == MEM_WRITE) |
810 |
idata = memory_readmax64(cpu, data, len); |
811 |
|
812 |
#if 0 |
813 |
/* Debug stuff useful when trying to make dev_asc compatible |
814 |
with the 'arc' emulation mode, which is different from |
815 |
the DECstation mode. */ |
816 |
fatal("[ asc: writeflag=%i addr=%08x idata=%016llx ]\n", |
817 |
writeflag, (int)relative_addr, (long long)idata); |
818 |
#endif |
819 |
|
820 |
switch (d->mode) { |
821 |
case DEV_ASC_DEC: |
822 |
regnr = relative_addr / 4; |
823 |
break; |
824 |
case DEV_ASC_PICA: |
825 |
default: |
826 |
regnr = relative_addr; |
827 |
} |
828 |
|
829 |
/* Controller's ID is fixed: */ |
830 |
d->reg_ro[NCR_CFG1] = (d->reg_ro[NCR_CFG1] & ~7) | ASC_SCSI_ID; |
831 |
|
832 |
d->reg_ro[NCR_FFLAG] = ((d->reg_ro[NCR_STEP] & 0x7) << 5) |
833 |
+ d->n_bytes_in_fifo; |
834 |
|
835 |
d->dma_address_reg = |
836 |
d->dma_address_reg_memory[0] + |
837 |
(d->dma_address_reg_memory[1] << 8) + |
838 |
(d->dma_address_reg_memory[2] << 16) + |
839 |
(d->dma_address_reg_memory[3] << 24); |
840 |
|
841 |
if (regnr < 0x10) { |
842 |
if (regnr == NCR_FIFO) { |
843 |
if (writeflag == MEM_WRITE) |
844 |
dev_asc_fifo_write(d, idata); |
845 |
else |
846 |
odata = dev_asc_fifo_read(d); |
847 |
} else { |
848 |
if (writeflag==MEM_WRITE) |
849 |
d->reg_wo[regnr] = idata; |
850 |
else |
851 |
odata = d->reg_ro[regnr]; |
852 |
} |
853 |
|
854 |
#ifdef ASC_FULL_REGISTER_ACCESS_DEBUG |
855 |
if (!quiet_mode) { |
856 |
if (writeflag==MEM_READ) { |
857 |
debug("[ asc: read from %s: 0x%02x", |
858 |
asc_reg_names[regnr], (int)odata); |
859 |
} else { |
860 |
debug("[ asc: write to %s: 0x%02x", |
861 |
asc_reg_names[regnr], (int)idata); |
862 |
} |
863 |
} |
864 |
#endif |
865 |
} else if (relative_addr >= 0x300 && relative_addr < 0x600 |
866 |
&& d->turbochannel != NULL) { |
867 |
debug("[ asc: offset 0x%x, redirecting to turbochannel" |
868 |
" access ]\n", relative_addr); |
869 |
return dev_turbochannel_access(cpu, mem, |
870 |
relative_addr, data, len, writeflag, |
871 |
d->turbochannel); |
872 |
} else { |
873 |
if (writeflag==MEM_READ) { |
874 |
fatal("[ asc: read from 0x%04x: 0x%02x ]\n", |
875 |
relative_addr, (int)odata); |
876 |
} else { |
877 |
fatal("[ asc: write to 0x%04x: 0x%02x ]\n", |
878 |
relative_addr, (int)idata); |
879 |
} |
880 |
} |
881 |
|
882 |
/* |
883 |
* Some registers are read/write. Copy contents of |
884 |
* reg_wo to reg_ro: |
885 |
*/ |
886 |
#if 0 |
887 |
d->reg_ro[ 0] = d->reg_wo[0]; /* Transfer count lo and */ |
888 |
d->reg_ro[ 1] = d->reg_wo[1]; /* middle */ |
889 |
#endif |
890 |
d->reg_ro[ 2] = d->reg_wo[2]; |
891 |
d->reg_ro[ 3] = d->reg_wo[3]; |
892 |
d->reg_ro[ 8] = d->reg_wo[8]; |
893 |
d->reg_ro[ 9] = d->reg_wo[9]; |
894 |
d->reg_ro[10] = d->reg_wo[10]; |
895 |
d->reg_ro[11] = d->reg_wo[11]; |
896 |
d->reg_ro[12] = d->reg_wo[12]; |
897 |
|
898 |
if (regnr == NCR_CMD && writeflag == MEM_WRITE) { |
899 |
if (!quiet_mode) |
900 |
debug(" "); |
901 |
|
902 |
/* TODO: Perhaps turn off others here too? */ |
903 |
d->reg_ro[NCR_INTR] &= ~NCRINTR_SBR; |
904 |
|
905 |
if (idata & NCRCMD_DMA) { |
906 |
if (!quiet_mode) |
907 |
debug("[DMA] "); |
908 |
|
909 |
/* |
910 |
* DMA commands load the transfer count from the |
911 |
* write-only registers to the read-only ones, and |
912 |
* the Terminal Count bit is cleared. |
913 |
*/ |
914 |
d->reg_ro[NCR_TCL] = d->reg_wo[NCR_TCL]; |
915 |
d->reg_ro[NCR_TCM] = d->reg_wo[NCR_TCM]; |
916 |
d->reg_ro[NCR_TCH] = d->reg_wo[NCR_TCH]; |
917 |
d->reg_ro[NCR_STAT] &= ~NCRSTAT_TC; |
918 |
} |
919 |
|
920 |
switch (idata & ~NCRCMD_DMA) { |
921 |
|
922 |
case NCRCMD_NOP: |
923 |
if (!quiet_mode) |
924 |
debug("NOP"); |
925 |
break; |
926 |
|
927 |
case NCRCMD_FLUSH: |
928 |
if (!quiet_mode) |
929 |
debug("FLUSH"); |
930 |
/* Flush the FIFO: */ |
931 |
dev_asc_fifo_flush(d); |
932 |
break; |
933 |
|
934 |
case NCRCMD_RSTCHIP: |
935 |
if (!quiet_mode) |
936 |
debug("RSTCHIP"); |
937 |
/* Hardware reset. */ |
938 |
dev_asc_reset(d); |
939 |
break; |
940 |
|
941 |
case NCRCMD_RSTSCSI: |
942 |
if (!quiet_mode) |
943 |
debug("RSTSCSI"); |
944 |
/* No interrupt if interrupts are disabled. */ |
945 |
if (!(d->reg_wo[NCR_CFG1] & NCRCFG1_SRR)) |
946 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
947 |
d->reg_ro[NCR_INTR] |= NCRINTR_SBR; |
948 |
d->reg_ro[NCR_INTR] |= NCRINTR_FC; |
949 |
d->cur_state = STATE_DISCONNECTED; |
950 |
break; |
951 |
|
952 |
case NCRCMD_ENSEL: |
953 |
if (!quiet_mode) |
954 |
debug("ENSEL"); |
955 |
/* TODO */ |
956 |
break; |
957 |
|
958 |
case NCRCMD_ICCS: |
959 |
if (!quiet_mode) |
960 |
debug("ICCS"); |
961 |
/* Reveice a status byte + a message byte. */ |
962 |
|
963 |
/* TODO: how about other status and message bytes? */ |
964 |
if (d->xferp != NULL && d->xferp->status != NULL) |
965 |
dev_asc_fifo_write(d, d->xferp->status[0]); |
966 |
else |
967 |
dev_asc_fifo_write(d, 0x00); |
968 |
|
969 |
if (d->xferp != NULL && d->xferp->msg_in != NULL) |
970 |
dev_asc_fifo_write(d, d->xferp->msg_in[0]); |
971 |
else |
972 |
dev_asc_fifo_write(d, 0x00); |
973 |
|
974 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
975 |
d->reg_ro[NCR_INTR] |= NCRINTR_FC; |
976 |
/* d->reg_ro[NCR_INTR] |= NCRINTR_BS; */ |
977 |
d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | 7; |
978 |
/* ? probably 7 */ |
979 |
d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | 4; |
980 |
/* ? */ |
981 |
break; |
982 |
|
983 |
case NCRCMD_MSGOK: |
984 |
/* Message is being Rejected if ATN is set, |
985 |
otherwise Accepted. */ |
986 |
if (!quiet_mode) { |
987 |
debug("MSGOK"); |
988 |
if (d->atn) |
989 |
debug("; Rejecting message"); |
990 |
else |
991 |
debug("; Accepting message"); |
992 |
} |
993 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
994 |
d->reg_ro[NCR_INTR] |= NCRINTR_DIS; |
995 |
|
996 |
d->reg_ro[NCR_STAT] = (d->reg_ro[NCR_STAT] & ~7) | |
997 |
d->cur_phase; /* 6? */ |
998 |
d->reg_ro[NCR_STEP] = (d->reg_ro[NCR_STEP] & ~7) | |
999 |
4; /* ? */ |
1000 |
|
1001 |
d->cur_state = STATE_DISCONNECTED; |
1002 |
|
1003 |
if (d->xferp != NULL) |
1004 |
scsi_transfer_free(d->xferp); |
1005 |
d->xferp = NULL; |
1006 |
break; |
1007 |
|
1008 |
case NCRCMD_SETATN: |
1009 |
if (!quiet_mode) |
1010 |
debug("SETATN"); |
1011 |
d->atn = 1; |
1012 |
break; |
1013 |
|
1014 |
case NCRCMD_RSTATN: |
1015 |
if (!quiet_mode) |
1016 |
debug("RSTATN"); |
1017 |
d->atn = 0; |
1018 |
break; |
1019 |
|
1020 |
case NCRCMD_SELNATN: |
1021 |
case NCRCMD_SELATN: |
1022 |
case NCRCMD_SELATNS: |
1023 |
case NCRCMD_SELATN3: |
1024 |
d->cur_phase = PHASE_COMMAND; |
1025 |
switch (idata & ~NCRCMD_DMA) { |
1026 |
case NCRCMD_SELATN: |
1027 |
case NCRCMD_SELATNS: |
1028 |
if ((idata & ~NCRCMD_DMA) == NCRCMD_SELATNS) { |
1029 |
if (!quiet_mode) |
1030 |
debug("SELATNS: select with " |
1031 |
"atn and stop, id %i", |
1032 |
d->reg_wo[NCR_SELID] & 7); |
1033 |
d->cur_phase = PHASE_MSG_OUT; |
1034 |
} else { |
1035 |
if (!quiet_mode) |
1036 |
debug("SELATN: select with atn" |
1037 |
", id %i", |
1038 |
d->reg_wo[NCR_SELID] & 7); |
1039 |
} |
1040 |
n_messagebytes = 1; |
1041 |
break; |
1042 |
case NCRCMD_SELATN3: |
1043 |
if (!quiet_mode) |
1044 |
debug("SELNATN: select with atn3, " |
1045 |
"id %i", d->reg_wo[NCR_SELID] & 7); |
1046 |
n_messagebytes = 3; |
1047 |
break; |
1048 |
case NCRCMD_SELNATN: |
1049 |
if (!quiet_mode) |
1050 |
debug("SELNATN: select without atn, " |
1051 |
"id %i", d->reg_wo[NCR_SELID] & 7); |
1052 |
n_messagebytes = 0; |
1053 |
} |
1054 |
|
1055 |
/* TODO: not just disk, but some generic |
1056 |
SCSI device */ |
1057 |
target_exists = diskimage_exist(cpu->machine, |
1058 |
d->reg_wo[NCR_SELID] & 7, DISKIMAGE_SCSI); |
1059 |
|
1060 |
if (target_exists) { |
1061 |
/* |
1062 |
* Select a SCSI device, send message bytes |
1063 |
* (if any) and command bytes to the target. |
1064 |
*/ |
1065 |
int ok; |
1066 |
|
1067 |
dev_asc_newxfer(d); |
1068 |
|
1069 |
ok = dev_asc_select(cpu, d, |
1070 |
d->reg_ro[NCR_CFG1] & 7, |
1071 |
d->reg_wo[NCR_SELID] & 7, |
1072 |
idata & NCRCMD_DMA? 1 : 0, |
1073 |
n_messagebytes); |
1074 |
|
1075 |
if (ok) |
1076 |
d->cur_state = STATE_INITIATOR; |
1077 |
else { |
1078 |
d->cur_state = STATE_DISCONNECTED; |
1079 |
d->reg_ro[NCR_INTR] |= NCRINTR_DIS; |
1080 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
1081 |
d->reg_ro[NCR_STEP] = |
1082 |
(d->reg_ro[NCR_STEP] & ~7) | 0; |
1083 |
if (d->xferp != NULL) |
1084 |
scsi_transfer_free(d->xferp); |
1085 |
d->xferp = NULL; |
1086 |
} |
1087 |
} else { |
1088 |
/* |
1089 |
* Selection failed, non-existant scsi ID: |
1090 |
* |
1091 |
* This is good enough to fool Ultrix, NetBSD, |
1092 |
* OpenBSD and Linux to continue detection of |
1093 |
* other IDs, without giving any warnings. |
1094 |
*/ |
1095 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
1096 |
d->reg_ro[NCR_INTR] |= NCRINTR_DIS; |
1097 |
d->reg_ro[NCR_STEP] &= ~7; |
1098 |
d->reg_ro[NCR_STEP] |= 0; |
1099 |
dev_asc_fifo_flush(d); |
1100 |
d->cur_state = STATE_DISCONNECTED; |
1101 |
} |
1102 |
break; |
1103 |
|
1104 |
case NCRCMD_TRPAD: |
1105 |
if (!quiet_mode) |
1106 |
debug("TRPAD"); |
1107 |
|
1108 |
dev_asc_newxfer(d); |
1109 |
{ |
1110 |
int ok; |
1111 |
|
1112 |
ok = dev_asc_transfer(cpu, d, |
1113 |
idata & NCRCMD_DMA? 1 : 0); |
1114 |
if (!ok) { |
1115 |
d->cur_state = STATE_DISCONNECTED; |
1116 |
d->reg_ro[NCR_INTR] |= NCRINTR_DIS; |
1117 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
1118 |
d->reg_ro[NCR_STEP] = (d->reg_ro[ |
1119 |
NCR_STEP] & ~7) | 0; |
1120 |
if (d->xferp != NULL) |
1121 |
scsi_transfer_free(d->xferp); |
1122 |
d->xferp = NULL; |
1123 |
} |
1124 |
} |
1125 |
break; |
1126 |
|
1127 |
/* Old code which didn't work with Mach: */ |
1128 |
#if 0 |
1129 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
1130 |
d->reg_ro[NCR_INTR] |= NCRINTR_BS; |
1131 |
d->reg_ro[NCR_INTR] |= NCRINTR_FC; |
1132 |
d->reg_ro[NCR_STAT] |= NCRSTAT_TC; |
1133 |
|
1134 |
d->reg_ro[NCR_TCL] = 0; |
1135 |
d->reg_ro[NCR_TCM] = 0; |
1136 |
|
1137 |
d->reg_ro[NCR_STEP] &= ~7; |
1138 |
#if 0 |
1139 |
d->reg_ro[NCR_STEP] |= 0; |
1140 |
dev_asc_fifo_flush(d); |
1141 |
#else |
1142 |
d->reg_ro[NCR_STEP] |= 4; |
1143 |
#endif |
1144 |
break; |
1145 |
#endif |
1146 |
|
1147 |
case NCRCMD_TRANS: |
1148 |
if (!quiet_mode) |
1149 |
debug("TRANS"); |
1150 |
|
1151 |
{ |
1152 |
int ok; |
1153 |
|
1154 |
ok = dev_asc_transfer(cpu, d, |
1155 |
idata & NCRCMD_DMA? 1 : 0); |
1156 |
if (!ok) { |
1157 |
d->cur_state = STATE_DISCONNECTED; |
1158 |
d->reg_ro[NCR_INTR] |= NCRINTR_DIS; |
1159 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
1160 |
d->reg_ro[NCR_STEP] = (d->reg_ro[ |
1161 |
NCR_STEP] & ~7) | 0; |
1162 |
if (d->xferp != NULL) |
1163 |
scsi_transfer_free(d->xferp); |
1164 |
d->xferp = NULL; |
1165 |
} |
1166 |
} |
1167 |
break; |
1168 |
|
1169 |
default: |
1170 |
fatal("(unimplemented asc cmd 0x%02x)", (int)idata); |
1171 |
d->reg_ro[NCR_STAT] |= NCRSTAT_INT; |
1172 |
d->reg_ro[NCR_INTR] |= NCRINTR_ILL; |
1173 |
/* |
1174 |
* TODO: exit or continue with Illegal command |
1175 |
* interrupt? |
1176 |
*/ |
1177 |
exit(1); |
1178 |
} |
1179 |
} |
1180 |
|
1181 |
if (regnr == NCR_INTR && writeflag == MEM_READ) { |
1182 |
/* |
1183 |
* Reading the interrupt register de-asserts the |
1184 |
* interrupt pin. Also, INTR, STEP, and STAT are all |
1185 |
* cleared, according to page 64 of the LSI53CF92A manual, |
1186 |
* if "interrupt output is true". |
1187 |
*/ |
1188 |
if (d->reg_ro[NCR_STAT] & NCRSTAT_INT) { |
1189 |
d->reg_ro[NCR_INTR] = 0; |
1190 |
d->reg_ro[NCR_STEP] = 0; |
1191 |
d->reg_ro[NCR_STAT] = 0; |
1192 |
|
1193 |
/* For Mach/PMAX? TODO */ |
1194 |
d->reg_ro[NCR_STAT] = PHASE_COMMAND; |
1195 |
} |
1196 |
|
1197 |
INTERRUPT_DEASSERT(d->irq); |
1198 |
d->irq_asserted = 0; |
1199 |
} |
1200 |
|
1201 |
if (regnr == NCR_CFG1) { |
1202 |
/* TODO: other bits */ |
1203 |
if (!quiet_mode) { |
1204 |
debug(" parity %s,", d->reg_ro[regnr] & |
1205 |
NCRCFG1_PARENB? "enabled" : "disabled"); |
1206 |
debug(" scsi_id %i", d->reg_ro[regnr] & 0x7); |
1207 |
} |
1208 |
} |
1209 |
|
1210 |
#ifdef ASC_FULL_REGISTER_ACCESS_DEBUG |
1211 |
debug(" ]\n"); |
1212 |
#endif |
1213 |
dev_asc_tick(cpu, extra); |
1214 |
|
1215 |
if (writeflag == MEM_READ) |
1216 |
memory_writemax64(cpu, data, len, odata); |
1217 |
|
1218 |
return 1; |
1219 |
} |
1220 |
|
1221 |
|
1222 |
/* |
1223 |
* dev_asc_init(): |
1224 |
* |
1225 |
* Register an 'asc' device. |
1226 |
*/ |
1227 |
void dev_asc_init(struct machine *machine, struct memory *mem, |
1228 |
uint64_t baseaddr, char *irq_path, void *turbochannel, int mode, |
1229 |
size_t (*dma_controller)(void *dma_controller_data, |
1230 |
unsigned char *data, size_t len, int writeflag), |
1231 |
void *dma_controller_data) |
1232 |
{ |
1233 |
struct asc_data *d; |
1234 |
|
1235 |
CHECK_ALLOCATION(d = malloc(sizeof(struct asc_data))); |
1236 |
memset(d, 0, sizeof(struct asc_data)); |
1237 |
|
1238 |
INTERRUPT_CONNECT(irq_path, d->irq); |
1239 |
d->turbochannel = turbochannel; |
1240 |
d->mode = mode; |
1241 |
|
1242 |
d->reg_ro[NCR_CFG3] = NCRF9XCFG3_CDB; |
1243 |
|
1244 |
CHECK_ALLOCATION(d->dma_address_reg_memory = |
1245 |
malloc(machine->arch_pagesize)); |
1246 |
memset(d->dma_address_reg_memory, 0, machine->arch_pagesize); |
1247 |
|
1248 |
CHECK_ALLOCATION(d->dma = malloc(ASC_DMA_SIZE)); |
1249 |
memset(d->dma, 0, ASC_DMA_SIZE); |
1250 |
|
1251 |
d->dma_controller = dma_controller; |
1252 |
d->dma_controller_data = dma_controller_data; |
1253 |
|
1254 |
memory_device_register(mem, "asc", baseaddr, |
1255 |
mode == DEV_ASC_PICA? DEV_ASC_PICA_LENGTH : DEV_ASC_DEC_LENGTH, |
1256 |
dev_asc_access, d, DM_DEFAULT, NULL); |
1257 |
|
1258 |
if (mode == DEV_ASC_DEC) { |
1259 |
memory_device_register(mem, "asc_dma_address_reg", |
1260 |
baseaddr + 0x40000, 4096, dev_asc_address_reg_access, d, |
1261 |
DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK, |
1262 |
(unsigned char *)&d->dma_address_reg_memory[0]); |
1263 |
memory_device_register(mem, "asc_dma", baseaddr + 0x80000, |
1264 |
ASC_DMA_SIZE, dev_asc_dma_access, d, |
1265 |
DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK, d->dma); |
1266 |
} |
1267 |
|
1268 |
machine_add_tickfunction(machine, dev_asc_tick, d, ASC_TICK_SHIFT); |
1269 |
} |
1270 |
|