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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_algor.c,v 1.3 2006/08/14 17:45:47 debug Exp $ |
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* |
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* Algor misc. stuff. |
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* |
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* TODO: This is hardcoded for P5064 right now. Generalize it to P40xx etc. |
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* |
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* CPU irq 2 = ISA, 3 = PCI, 4 = Local. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "algor_p5064reg.h" |
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|
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|
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DEVICE_ACCESS(algor) |
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{ |
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struct algor_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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char *n = NULL; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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relative_addr += d->base_addr; |
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|
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switch (relative_addr) { |
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|
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case P5064_LED1 + 0x0: |
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case P5064_LED1 + 0x4: |
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case P5064_LED1 + 0x8: |
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case P5064_LED1 + 0xc: |
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break; |
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|
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case P5064_LOCINT: |
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/* |
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* TODO: See how ISAINT is implemented. |
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* |
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* Implemented so far: COM1 only. |
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*/ |
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n = "P5064_LOCINT"; |
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if (writeflag == MEM_READ) { |
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/* Ugly hack for NetBSD startup. TODO: fix */ |
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static int x = 0; |
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if (((++ x) & 0xffff) == 0) |
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odata |= LOCINT_RTC; |
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|
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if (cpu->machine->isa_pic_data.pic1->irr & |
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~cpu->machine->isa_pic_data.pic1->ier & 0x10) |
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odata |= LOCINT_COM1; |
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if (cpu->machine->isa_pic_data.pic1->irr & |
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~cpu->machine->isa_pic_data.pic1->ier & 0x08) |
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odata |= LOCINT_COM2; |
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|
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/* Read => ack: */ |
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cpu->machine->isa_pic_data.pic1->irr &= ~0x18; |
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cpu_interrupt_ack(cpu, 4); |
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} else { |
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if (idata & LOCINT_COM1) |
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cpu->machine->isa_pic_data.pic1->ier &= ~0x10; |
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else |
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cpu->machine->isa_pic_data.pic1->ier |= 0x10; |
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if (idata & LOCINT_COM2) |
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cpu->machine->isa_pic_data.pic1->ier &= ~0x08; |
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else |
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cpu->machine->isa_pic_data.pic1->ier |= 0x08; |
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} |
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break; |
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|
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case P5064_PANIC: |
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n = "P5064_PANIC"; |
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if (writeflag == MEM_READ) |
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odata = 0; |
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break; |
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|
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case P5064_PCIINT: |
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/* |
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* TODO: See how ISAINT is implemented. |
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*/ |
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n = "P5064_PCIINT"; |
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if (writeflag == MEM_READ) { |
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odata = 0; |
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cpu_interrupt_ack(cpu, 3); |
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} |
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break; |
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|
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case P5064_ISAINT: |
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/* |
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* ISA interrupts: |
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* |
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* Bit: IRQ Source: |
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* 0 ISAINT_ISABR |
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* 1 ISAINT_IDE0 |
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* 2 ISAINT_IDE1 |
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* |
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* NOTE/TODO: Ugly redirection to the ISA controller. |
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*/ |
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n = "P5064_ISAINT"; |
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if (writeflag == MEM_WRITE) { |
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if (idata & ISAINT_IDE0) |
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cpu->machine->isa_pic_data.pic2->ier &= ~0x40; |
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else |
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cpu->machine->isa_pic_data.pic2->ier |= 0x40; |
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if (idata & ISAINT_IDE1) |
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cpu->machine->isa_pic_data.pic2->ier &= ~0x80; |
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else |
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cpu->machine->isa_pic_data.pic2->ier |= 0x80; |
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cpu->machine->isa_pic_data.pic1->ier &= ~0x04; |
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} else { |
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if (cpu->machine->isa_pic_data.pic2->irr & |
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~cpu->machine->isa_pic_data.pic2->ier & 0x40) |
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odata |= ISAINT_IDE0; |
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if (cpu->machine->isa_pic_data.pic2->irr & |
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~cpu->machine->isa_pic_data.pic2->ier & 0x80) |
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odata |= ISAINT_IDE1; |
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|
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/* Read => ack: */ |
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cpu->machine->isa_pic_data.pic2->irr &= ~0xc0; |
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cpu_interrupt_ack(cpu, 2); |
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} |
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break; |
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|
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case P5064_KBDINT: |
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/* |
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* TODO: See how ISAINT is implemented. |
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*/ |
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n = "P5064_KBDINT"; |
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if (writeflag == MEM_READ) |
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odata = 0; |
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break; |
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|
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default:if (writeflag == MEM_READ) { |
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fatal("[ algor: read from 0x%x ]\n", |
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(int)relative_addr); |
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} else { |
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fatal("[ algor: write to 0x%x: 0x%"PRIx64" ]\n", |
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(int) relative_addr, (uint64_t) idata); |
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} |
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} |
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|
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if (n != NULL) { |
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if (writeflag == MEM_READ) { |
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debug("[ algor: read from %s: 0x%"PRIx64" ]\n", |
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n, (uint64_t) odata); |
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} else { |
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debug("[ algor: write to %s: 0x%"PRIx64" ]\n", |
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n, (uint64_t) idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(algor) |
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{ |
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struct algor_data *d = malloc(sizeof(struct algor_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct algor_data)); |
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|
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if (devinit->addr != 0x1ff00000) { |
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fatal("The Algor base address should be 0x1ff00000.\n"); |
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exit(1); |
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} |
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|
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memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL); |
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|
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d->base_addr = devinit->addr; |
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|
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devinit->return_ptr = d; |
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|
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return 1; |
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} |
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