/[gxemul]/trunk/src/devices/dev_algor.c
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revision 30 by dpavlin, Mon Oct 8 16:20:40 2007 UTC revision 34 by dpavlin, Mon Oct 8 16:21:17 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: dev_algor.c,v 1.3 2006/08/14 17:45:47 debug Exp $   *  $Id: dev_algor.c,v 1.5 2007/01/20 13:26:20 debug Exp $
29   *   *
30   *  Algor misc. stuff.   *  Algor misc. stuff.
31   *   *
# Line 41  Line 41 
41  #include "cpu.h"  #include "cpu.h"
42  #include "device.h"  #include "device.h"
43  #include "devices.h"  #include "devices.h"
44    #include "interrupt.h"
45  #include "machine.h"  #include "machine.h"
46  #include "memory.h"  #include "memory.h"
47  #include "misc.h"  #include "misc.h"
# Line 48  Line 49 
49  #include "algor_p5064reg.h"  #include "algor_p5064reg.h"
50    
51    
52    struct algor_data {
53            uint64_t                base_addr;
54            struct interrupt        mips_irq_2;
55            struct interrupt        mips_irq_3;
56            struct interrupt        mips_irq_4;
57    };
58    
59    
60  DEVICE_ACCESS(algor)  DEVICE_ACCESS(algor)
61  {  {
62          struct algor_data *d = extra;          struct algor_data *d = extra;
# Line 89  DEVICE_ACCESS(algor) Line 98  DEVICE_ACCESS(algor)
98    
99                          /*  Read => ack:  */                          /*  Read => ack:  */
100                          cpu->machine->isa_pic_data.pic1->irr &= ~0x18;                          cpu->machine->isa_pic_data.pic1->irr &= ~0x18;
101                          cpu_interrupt_ack(cpu, 4);                          INTERRUPT_DEASSERT(d->mips_irq_4);
102                  } else {                  } else {
103                          if (idata & LOCINT_COM1)                          if (idata & LOCINT_COM1)
104                                  cpu->machine->isa_pic_data.pic1->ier &= ~0x10;                                  cpu->machine->isa_pic_data.pic1->ier &= ~0x10;
# Line 115  DEVICE_ACCESS(algor) Line 124  DEVICE_ACCESS(algor)
124                  n = "P5064_PCIINT";                  n = "P5064_PCIINT";
125                  if (writeflag == MEM_READ) {                  if (writeflag == MEM_READ) {
126                          odata = 0;                          odata = 0;
127                          cpu_interrupt_ack(cpu, 3);                          INTERRUPT_DEASSERT(d->mips_irq_3);
128                  }                  }
129                  break;                  break;
130    
# Line 151  DEVICE_ACCESS(algor) Line 160  DEVICE_ACCESS(algor)
160    
161                          /*  Read => ack:  */                          /*  Read => ack:  */
162                          cpu->machine->isa_pic_data.pic2->irr &= ~0xc0;                          cpu->machine->isa_pic_data.pic2->irr &= ~0xc0;
163                          cpu_interrupt_ack(cpu, 2);                          INTERRUPT_DEASSERT(d->mips_irq_2);
164                  }                  }
165                  break;                  break;
166    
# Line 192  DEVICE_ACCESS(algor) Line 201  DEVICE_ACCESS(algor)
201    
202  DEVINIT(algor)  DEVINIT(algor)
203  {  {
204            char tmpstr[200];
205          struct algor_data *d = malloc(sizeof(struct algor_data));          struct algor_data *d = malloc(sizeof(struct algor_data));
206          if (d == NULL) {          if (d == NULL) {
207                  fprintf(stderr, "out of memory\n");                  fprintf(stderr, "out of memory\n");
# Line 199  DEVINIT(algor) Line 209  DEVINIT(algor)
209          }          }
210          memset(d, 0, sizeof(struct algor_data));          memset(d, 0, sizeof(struct algor_data));
211    
212            d->base_addr = devinit->addr;
213          if (devinit->addr != 0x1ff00000) {          if (devinit->addr != 0x1ff00000) {
214                  fatal("The Algor base address should be 0x1ff00000.\n");                  fatal("The Algor base address should be 0x1ff00000.\n");
215                  exit(1);                  exit(1);
216          }          }
217    
218            /*  Connect to MIPS irq 2, 3, and 4:  */
219            snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
220            INTERRUPT_CONNECT(tmpstr, d->mips_irq_2);
221            snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
222            INTERRUPT_CONNECT(tmpstr, d->mips_irq_3);
223            snprintf(tmpstr, sizeof(tmpstr), "%s.4", devinit->interrupt_path);
224            INTERRUPT_CONNECT(tmpstr, d->mips_irq_4);
225    
226          memory_device_register(devinit->machine->memory, devinit->name,          memory_device_register(devinit->machine->memory, devinit->name,
227              devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL);              devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL);
228    
         d->base_addr = devinit->addr;  
   
229          devinit->return_ptr = d;          devinit->return_ptr = d;
230    
231          return 1;          return 1;
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