/[gxemul]/trunk/src/devices/dev_algor.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/devices/dev_algor.c

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Revision 30 - (hide annotations)
Mon Oct 8 16:20:40 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 5704 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1325 2006/08/15 15:38:37 debug Exp $
20060723	More Transputer instructions (pfix, nfix, opr, mint, ldl, ldlp,
		eqc, rev, ajw, stl, stlf, sthf, sub, ldnl, ldnlp, ldpi, move,
		wcnt, add, bcnt).
		Adding more SPARC instructions (andcc, addcc, bl, rdpr).
		Progress on the igsfb framebuffer used by NetBSD/netwinder.
		Enabling 8-bit fills in dev_fb.
		NetBSD/netwinder 3.0.1 can now run from a disk image :-)
20060724	Cleanup/performance fix for 64-bit virtual translation table
		updates (by removing the "timestamp" stuff). A full NetBSD/pmax
		3.0.1 install for R4400 has dropped from 667 seconds to 584 :)
		Fixing the igsfb "almost vga" color (it is 24-bit, not 18-bit).
		Adding some MIPS instruction combinations (3*lw, and 3*addu).
		The 8048 keyboard now turns off interrupt enable between the
		KBR_ACK and the KBR_RSTDONE, to work better with Linux 2.6.
		Not causing PPC DEC interrupts if PPC_NO_DEC is set for a
		specific CPU; NetBSD/bebox gets slightly further than before.
		Adding some more SPARC instructions: branches, udiv.
20060725	Refreshing dev_pckbc.c a little.
		Cleanups for the SH emulation mode, and adding the first
		"compact" (16-bit) instructions: various simple movs, nop,
		shll, stc, or, ldc.
20060726	Adding dummy "pcn" (AMD PCnet NIC) PCI glue.
20060727	Various cleanups; removing stuff from cpu.h, such as
		running_translated (not really meaningful anymore), and
		page flags (breaking into the debugger clears all translations
		anyway).
		Minor MIPS instruction combination updates.
20060807	Expanding the 3*sw and 3*lw MIPS instruction combinations to
		work with 2* and 4* too, resulting in a minor performance gain.
		Implementing a usleep hack for the RM52xx/MIPS32/MIPS64 "wait"
		instruction (when emulating 1 cpu).
20060808	Experimenting with some more MIPS instruction combinations.
		Implementing support for showing a (hardcoded 12x22) text
		cursor in igsfb.
20060809	Simplifying the NetBSD/evbmips (Malta) install instructions
		somewhat (by using a NetBSD/pmax ramdisk install kernel).
20060812	Experimenting more with the MIPS 'wait' instruction.
		PCI configuration register writes can now be handled, which
		allow PCI IDE controllers to work with NetBSD/Malta 3.0.1 and
		NetBSD/cobalt 3.0.1. (Previously only NetBSD 2.1 worked.)
20060813	Updating dev_gt.c based on numbers from Alec Voropay, to enable
		Linux 2.6 to use PCI on Malta.
		Continuing on Algor interrupt stuff.
20060814	Adding support for routing ISA interrupts to two different
		interrupts, making it possible to run NetBSD/algor :-)
20060814-15	Testing for the release.

==============  RELEASE 0.4.2  ==============
1 dpavlin 22 /*
2     * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 30 * $Id: dev_algor.c,v 1.3 2006/08/14 17:45:47 debug Exp $
29 dpavlin 22 *
30     * Algor misc. stuff.
31     *
32     * TODO: This is hardcoded for P5064 right now. Generalize it to P40xx etc.
33 dpavlin 30 *
34     * CPU irq 2 = ISA, 3 = PCI, 4 = Local.
35 dpavlin 22 */
36    
37     #include <stdio.h>
38     #include <stdlib.h>
39     #include <string.h>
40    
41     #include "cpu.h"
42     #include "device.h"
43     #include "devices.h"
44     #include "machine.h"
45     #include "memory.h"
46     #include "misc.h"
47    
48     #include "algor_p5064reg.h"
49    
50    
51     DEVICE_ACCESS(algor)
52     {
53     struct algor_data *d = extra;
54     uint64_t idata = 0, odata = 0;
55     char *n = NULL;
56    
57     if (writeflag == MEM_WRITE)
58     idata = memory_readmax64(cpu, data, len);
59    
60     relative_addr += d->base_addr;
61    
62     switch (relative_addr) {
63    
64 dpavlin 30 case P5064_LED1 + 0x0:
65     case P5064_LED1 + 0x4:
66     case P5064_LED1 + 0x8:
67     case P5064_LED1 + 0xc:
68     break;
69    
70 dpavlin 22 case P5064_LOCINT:
71 dpavlin 30 /*
72     * TODO: See how ISAINT is implemented.
73     *
74     * Implemented so far: COM1 only.
75     */
76     n = "P5064_LOCINT";
77     if (writeflag == MEM_READ) {
78     /* Ugly hack for NetBSD startup. TODO: fix */
79 dpavlin 22 static int x = 0;
80 dpavlin 30 if (((++ x) & 0xffff) == 0)
81 dpavlin 22 odata |= LOCINT_RTC;
82 dpavlin 30
83     if (cpu->machine->isa_pic_data.pic1->irr &
84     ~cpu->machine->isa_pic_data.pic1->ier & 0x10)
85     odata |= LOCINT_COM1;
86     if (cpu->machine->isa_pic_data.pic1->irr &
87     ~cpu->machine->isa_pic_data.pic1->ier & 0x08)
88     odata |= LOCINT_COM2;
89    
90     /* Read => ack: */
91     cpu->machine->isa_pic_data.pic1->irr &= ~0x18;
92     cpu_interrupt_ack(cpu, 4);
93     } else {
94     if (idata & LOCINT_COM1)
95     cpu->machine->isa_pic_data.pic1->ier &= ~0x10;
96     else
97     cpu->machine->isa_pic_data.pic1->ier |= 0x10;
98     if (idata & LOCINT_COM2)
99     cpu->machine->isa_pic_data.pic1->ier &= ~0x08;
100     else
101     cpu->machine->isa_pic_data.pic1->ier |= 0x08;
102 dpavlin 22 }
103     break;
104    
105 dpavlin 30 case P5064_PANIC:
106     n = "P5064_PANIC";
107     if (writeflag == MEM_READ)
108     odata = 0;
109     break;
110    
111     case P5064_PCIINT:
112     /*
113     * TODO: See how ISAINT is implemented.
114     */
115     n = "P5064_PCIINT";
116     if (writeflag == MEM_READ) {
117     odata = 0;
118     cpu_interrupt_ack(cpu, 3);
119     }
120     break;
121    
122     case P5064_ISAINT:
123     /*
124     * ISA interrupts:
125     *
126     * Bit: IRQ Source:
127     * 0 ISAINT_ISABR
128     * 1 ISAINT_IDE0
129     * 2 ISAINT_IDE1
130     *
131     * NOTE/TODO: Ugly redirection to the ISA controller.
132     */
133     n = "P5064_ISAINT";
134     if (writeflag == MEM_WRITE) {
135     if (idata & ISAINT_IDE0)
136     cpu->machine->isa_pic_data.pic2->ier &= ~0x40;
137     else
138     cpu->machine->isa_pic_data.pic2->ier |= 0x40;
139     if (idata & ISAINT_IDE1)
140     cpu->machine->isa_pic_data.pic2->ier &= ~0x80;
141     else
142     cpu->machine->isa_pic_data.pic2->ier |= 0x80;
143     cpu->machine->isa_pic_data.pic1->ier &= ~0x04;
144     } else {
145     if (cpu->machine->isa_pic_data.pic2->irr &
146     ~cpu->machine->isa_pic_data.pic2->ier & 0x40)
147     odata |= ISAINT_IDE0;
148     if (cpu->machine->isa_pic_data.pic2->irr &
149     ~cpu->machine->isa_pic_data.pic2->ier & 0x80)
150     odata |= ISAINT_IDE1;
151    
152     /* Read => ack: */
153     cpu->machine->isa_pic_data.pic2->irr &= ~0xc0;
154     cpu_interrupt_ack(cpu, 2);
155     }
156     break;
157    
158     case P5064_KBDINT:
159     /*
160     * TODO: See how ISAINT is implemented.
161     */
162     n = "P5064_KBDINT";
163     if (writeflag == MEM_READ)
164     odata = 0;
165     break;
166    
167 dpavlin 22 default:if (writeflag == MEM_READ) {
168     fatal("[ algor: read from 0x%x ]\n",
169     (int)relative_addr);
170     } else {
171 dpavlin 24 fatal("[ algor: write to 0x%x: 0x%"PRIx64" ]\n",
172     (int) relative_addr, (uint64_t) idata);
173 dpavlin 22 }
174     }
175    
176     if (n != NULL) {
177     if (writeflag == MEM_READ) {
178 dpavlin 30 debug("[ algor: read from %s: 0x%"PRIx64" ]\n",
179     n, (uint64_t) odata);
180 dpavlin 22 } else {
181 dpavlin 24 debug("[ algor: write to %s: 0x%"PRIx64" ]\n",
182     n, (uint64_t) idata);
183 dpavlin 22 }
184     }
185    
186     if (writeflag == MEM_READ)
187     memory_writemax64(cpu, data, len, odata);
188    
189     return 1;
190     }
191    
192    
193     DEVINIT(algor)
194     {
195     struct algor_data *d = malloc(sizeof(struct algor_data));
196     if (d == NULL) {
197     fprintf(stderr, "out of memory\n");
198     exit(1);
199     }
200     memset(d, 0, sizeof(struct algor_data));
201    
202     if (devinit->addr != 0x1ff00000) {
203     fatal("The Algor base address should be 0x1ff00000.\n");
204     exit(1);
205     }
206    
207     memory_device_register(devinit->machine->memory, devinit->name,
208     devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL);
209    
210     d->base_addr = devinit->addr;
211    
212     devinit->return_ptr = d;
213    
214     return 1;
215     }
216    
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