/[gxemul]/trunk/src/devices/dev_ahc.c
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Annotation of /trunk/src/devices/dev_ahc.c

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 3 months ago) by dpavlin
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File size: 5373 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 dpavlin 20 /*
2 dpavlin 22 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 dpavlin 20 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 28 * $Id: dev_ahc.c,v 1.5 2006/07/21 16:55:41 debug Exp $
29 dpavlin 20 *
30     * Adaptec AHC SCSI controller.
31     *
32     * NetBSD should say something like this, on SGI-IP32:
33     * ahc0 at pci0 dev 1 function 0
34     * ahc0: interrupting at crime irq 0
35     * ahc0: aic7880 Wide Channel A, SCSI Id=7, 16/255 SCBs
36     * ahc0: Host Adapter Bios disabled. Using default SCSI device parameters
37     *
38     * TODO: This more or less just a dummy device, so far.
39     */
40    
41     #include <stdio.h>
42     #include <stdlib.h>
43     #include <string.h>
44    
45     #include "cpu.h"
46     #include "device.h"
47     #include "machine.h"
48     #include "memory.h"
49     #include "misc.h"
50    
51     #include "aic7xxx_reg.h"
52    
53    
54     /* #define AHC_DEBUG
55     #define debug fatal */
56    
57    
58     #define DEV_AHC_LENGTH 0x100
59    
60     struct ahc_data {
61     unsigned char reg[DEV_AHC_LENGTH];
62     };
63    
64    
65 dpavlin 22 DEVICE_ACCESS(ahc)
66 dpavlin 20 {
67     struct ahc_data *d = extra;
68     uint64_t idata, odata = 0;
69     int ok = 0;
70     char *name = NULL;
71    
72     idata = memory_readmax64(cpu, data, len);
73    
74     /* YUCK! SGI uses reversed order inside 32-bit words: */
75     if (cpu->byte_order == EMUL_BIG_ENDIAN)
76     relative_addr = (relative_addr & ~0x3)
77     | (3 - (relative_addr & 3));
78    
79     relative_addr %= DEV_AHC_LENGTH;
80    
81     if (len != 1)
82     fatal("[ ahc: ERROR! Unimplemented len %i ]\n", len);
83    
84     if (writeflag == MEM_READ)
85     odata = d->reg[relative_addr];
86    
87     switch (relative_addr) {
88    
89     case SCSIID:
90     if (writeflag == MEM_READ) {
91     ok = 1; name = "SCSIID";
92     odata = 0;
93     } else {
94     fatal("[ ahc: write to SCSIOFFSET, data = 0x"
95     "%02x: TODO ]\n", (int)idata);
96     }
97     break;
98    
99     case KERNEL_QINPOS:
100     if (writeflag == MEM_WRITE) {
101    
102     /* TODO */
103    
104     d->reg[INTSTAT] |= SEQINT;
105     }
106     break;
107    
108     case SEECTL:
109     ok = 1; name = "SEECTL";
110     if (writeflag == MEM_WRITE)
111     d->reg[relative_addr] = idata;
112     odata |= SEERDY;
113     break;
114    
115     case SCSICONF:
116     ok = 1; name = "SCSICONF";
117     if (writeflag == MEM_READ) {
118     odata = 0;
119     } else {
120     fatal("[ ahc: write to SCSICONF, data = 0x%02x:"
121     " TODO ]\n", (int)idata);
122     }
123     break;
124    
125     case SEQRAM:
126     case SEQADDR0:
127     case SEQADDR1:
128     /* TODO: This is just a dummy. */
129     break;
130    
131     case HCNTRL:
132     ok = 1; name = "HCNTRL";
133     if (writeflag == MEM_WRITE)
134     d->reg[relative_addr] = idata;
135     break;
136    
137     case INTSTAT:
138     ok = 1; name = "INTSTAT";
139     if (writeflag == MEM_WRITE)
140     fatal("[ ahc: write to INTSTAT? data = 0x%02x ]\n",
141     (int)idata);
142     break;
143    
144     case CLRINT:
145     if (writeflag == MEM_READ) {
146     ok = 1; name = "ERROR";
147     /* TODO */
148     } else {
149     ok = 1; name = "CLRINT";
150     if (idata & ~0xf)
151     fatal("[ ahc: write to CLRINT: 0x%02x "
152     "(TODO) ]\n", (int)idata);
153     /* Clear the lowest 4 bits of intstat: */
154     d->reg[INTSTAT] &= ~(idata & 0xf);
155     }
156     break;
157    
158     default:
159     if (writeflag == MEM_WRITE)
160     fatal("[ ahc: UNIMPLEMENTED write to address 0x%x, "
161     "data=0x%02x ]\n", (int)relative_addr, (int)idata);
162     else
163     fatal("[ ahc: UNIMPLEMENTED read from address 0x%x ]\n",
164     (int)relative_addr);
165     }
166    
167     #if 0
168     cpu_interrupt(cpu, 0x200);
169     #endif
170    
171     #ifdef AHC_DEBUG
172     if (ok) {
173     if (name == NULL) {
174     if (writeflag == MEM_WRITE)
175     debug("[ ahc: write to address 0x%x: 0x"
176     "%02x ]\n", (int)relative_addr, (int)idata);
177     else
178     debug("[ ahc: read from address 0x%x: 0x"
179     "%02x ]\n", (int)relative_addr, (int)odata);
180     } else {
181     if (writeflag == MEM_WRITE)
182     debug("[ ahc: write to %s: 0x%02x ]\n",
183     name, (int)idata);
184     else
185     debug("[ ahc: read from %s: 0x%02x ]\n",
186     name, (int)odata);
187     }
188     }
189     #endif
190    
191     if (writeflag == MEM_READ)
192     memory_writemax64(cpu, data, len, odata);
193    
194     return 1;
195     }
196    
197    
198 dpavlin 22 DEVINIT(ahc)
199 dpavlin 20 {
200     struct ahc_data *d = malloc(sizeof(struct ahc_data));
201     if (d == NULL) {
202     fprintf(stderr, "out of memory\n");
203     exit(1);
204     }
205     memset(d, 0, sizeof(struct ahc_data));
206    
207     memory_device_register(devinit->machine->memory, devinit->name,
208     devinit->addr, DEV_AHC_LENGTH, dev_ahc_access, d,
209     DM_DEFAULT, NULL);
210    
211     return 1;
212     }
213    

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