/[gxemul]/trunk/src/devices/dev_ahc.c
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Annotation of /trunk/src/devices/dev_ahc.c

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Mon Oct 8 16:19:37 2007 UTC (13 years, 3 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 20 /*
2 dpavlin 22 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 dpavlin 20 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 22 * $Id: dev_ahc.c,v 1.4 2006/02/09 20:02:59 debug Exp $
29 dpavlin 20 *
30     * Adaptec AHC SCSI controller.
31     *
32     * NetBSD should say something like this, on SGI-IP32:
33     * ahc0 at pci0 dev 1 function 0
34     * ahc0: interrupting at crime irq 0
35     * ahc0: aic7880 Wide Channel A, SCSI Id=7, 16/255 SCBs
36     * ahc0: Host Adapter Bios disabled. Using default SCSI device parameters
37     *
38     * TODO: This more or less just a dummy device, so far.
39     */
40    
41     #include <stdio.h>
42     #include <stdlib.h>
43     #include <string.h>
44    
45     #include "cpu.h"
46     #include "device.h"
47     #include "machine.h"
48     #include "memory.h"
49     #include "misc.h"
50    
51     #include "aic7xxx_reg.h"
52    
53    
54     /* #define AHC_DEBUG
55     #define debug fatal */
56    
57    
58     #define DEV_AHC_LENGTH 0x100
59    
60     struct ahc_data {
61     unsigned char reg[DEV_AHC_LENGTH];
62     };
63    
64    
65     /*
66     * dev_ahc_access():
67     */
68 dpavlin 22 DEVICE_ACCESS(ahc)
69 dpavlin 20 {
70     struct ahc_data *d = extra;
71     uint64_t idata, odata = 0;
72     int ok = 0;
73     char *name = NULL;
74    
75     idata = memory_readmax64(cpu, data, len);
76    
77     /* YUCK! SGI uses reversed order inside 32-bit words: */
78     if (cpu->byte_order == EMUL_BIG_ENDIAN)
79     relative_addr = (relative_addr & ~0x3)
80     | (3 - (relative_addr & 3));
81    
82     relative_addr %= DEV_AHC_LENGTH;
83    
84     if (len != 1)
85     fatal("[ ahc: ERROR! Unimplemented len %i ]\n", len);
86    
87     if (writeflag == MEM_READ)
88     odata = d->reg[relative_addr];
89    
90     switch (relative_addr) {
91    
92     case SCSIID:
93     if (writeflag == MEM_READ) {
94     ok = 1; name = "SCSIID";
95     odata = 0;
96     } else {
97     fatal("[ ahc: write to SCSIOFFSET, data = 0x"
98     "%02x: TODO ]\n", (int)idata);
99     }
100     break;
101    
102     case KERNEL_QINPOS:
103     if (writeflag == MEM_WRITE) {
104    
105     /* TODO */
106    
107     d->reg[INTSTAT] |= SEQINT;
108     }
109     break;
110    
111     case SEECTL:
112     ok = 1; name = "SEECTL";
113     if (writeflag == MEM_WRITE)
114     d->reg[relative_addr] = idata;
115     odata |= SEERDY;
116     break;
117    
118     case SCSICONF:
119     ok = 1; name = "SCSICONF";
120     if (writeflag == MEM_READ) {
121     odata = 0;
122     } else {
123     fatal("[ ahc: write to SCSICONF, data = 0x%02x:"
124     " TODO ]\n", (int)idata);
125     }
126     break;
127    
128     case SEQRAM:
129     case SEQADDR0:
130     case SEQADDR1:
131     /* TODO: This is just a dummy. */
132     break;
133    
134     case HCNTRL:
135     ok = 1; name = "HCNTRL";
136     if (writeflag == MEM_WRITE)
137     d->reg[relative_addr] = idata;
138     break;
139    
140     case INTSTAT:
141     ok = 1; name = "INTSTAT";
142     if (writeflag == MEM_WRITE)
143     fatal("[ ahc: write to INTSTAT? data = 0x%02x ]\n",
144     (int)idata);
145     break;
146    
147     case CLRINT:
148     if (writeflag == MEM_READ) {
149     ok = 1; name = "ERROR";
150     /* TODO */
151     } else {
152     ok = 1; name = "CLRINT";
153     if (idata & ~0xf)
154     fatal("[ ahc: write to CLRINT: 0x%02x "
155     "(TODO) ]\n", (int)idata);
156     /* Clear the lowest 4 bits of intstat: */
157     d->reg[INTSTAT] &= ~(idata & 0xf);
158     }
159     break;
160    
161     default:
162     if (writeflag == MEM_WRITE)
163     fatal("[ ahc: UNIMPLEMENTED write to address 0x%x, "
164     "data=0x%02x ]\n", (int)relative_addr, (int)idata);
165     else
166     fatal("[ ahc: UNIMPLEMENTED read from address 0x%x ]\n",
167     (int)relative_addr);
168     }
169    
170     #if 0
171     cpu_interrupt(cpu, 0x200);
172     #endif
173    
174     #ifdef AHC_DEBUG
175     if (ok) {
176     if (name == NULL) {
177     if (writeflag == MEM_WRITE)
178     debug("[ ahc: write to address 0x%x: 0x"
179     "%02x ]\n", (int)relative_addr, (int)idata);
180     else
181     debug("[ ahc: read from address 0x%x: 0x"
182     "%02x ]\n", (int)relative_addr, (int)odata);
183     } else {
184     if (writeflag == MEM_WRITE)
185     debug("[ ahc: write to %s: 0x%02x ]\n",
186     name, (int)idata);
187     else
188     debug("[ ahc: read from %s: 0x%02x ]\n",
189     name, (int)odata);
190     }
191     }
192     #endif
193    
194     if (writeflag == MEM_READ)
195     memory_writemax64(cpu, data, len, odata);
196    
197     return 1;
198     }
199    
200    
201 dpavlin 22 DEVINIT(ahc)
202 dpavlin 20 {
203     struct ahc_data *d = malloc(sizeof(struct ahc_data));
204     if (d == NULL) {
205     fprintf(stderr, "out of memory\n");
206     exit(1);
207     }
208     memset(d, 0, sizeof(struct ahc_data));
209    
210     memory_device_register(devinit->machine->memory, devinit->name,
211     devinit->addr, DEV_AHC_LENGTH, dev_ahc_access, d,
212     DM_DEFAULT, NULL);
213    
214     return 1;
215     }
216    

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