/[gxemul]/trunk/src/devices/dev_8259.c
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Contents of /trunk/src/devices/dev_8259.c

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Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 7740 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_8259.c,v 1.25 2006/07/21 16:55:41 debug Exp $
29 *
30 * 8259 Programmable Interrupt Controller.
31 *
32 * See the following URL for more details:
33 * http://www.nondot.org/sabre/os/files/MiscHW/8259pic.txt
34 */
35
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39
40 #include "cpu.h"
41 #include "device.h"
42 #include "devices.h"
43 #include "emul.h"
44 #include "machine.h"
45 #include "memory.h"
46 #include "misc.h"
47
48
49 #define DEV_8259_LENGTH 2
50
51 /* #define DEV_8259_DEBUG */
52
53
54 DEVICE_ACCESS(8259)
55 {
56 struct pic8259_data *d = (struct pic8259_data *) extra;
57 uint64_t idata = 0, odata = 0;
58 int i;
59
60 if (writeflag == MEM_WRITE)
61 idata = memory_readmax64(cpu, data, len);
62
63 #ifdef DEV_8259_DEBUG
64 if (writeflag == MEM_READ)
65 fatal("[ 8259: read from 0x%x ]\n", (int)relative_addr);
66 else
67 fatal("[ 8259: write to 0x%x: 0x%x ]\n",
68 (int)relative_addr, (int)idata);
69 #endif
70
71 switch (relative_addr) {
72 case 0x00:
73 if (writeflag == MEM_WRITE) {
74 if ((idata & 0x10) == 0x10) {
75 /* Bit 3: 0=edge, 1=level */
76 if (idata & 0x08)
77 fatal("[ 8259: TODO: Level "
78 "triggered (MCA bus) ]\n");
79 if (idata & 0x04)
80 fatal("[ 8259: WARNING: Bit 2 set ]\n");
81 /* Bit 1: 0=cascade, 1=single */
82 /* Bit 0: 1=4th init byte */
83 /* This happens on non-x86 systems:
84 if (!(idata & 0x01))
85 fatal("[ 8259: WARNING: Bit 0 NOT set!"
86 "!! ]\n"); */
87 d->init_state = 1;
88 break;
89 }
90
91 /* TODO: Is it ok to abort init state when there
92 is a non-init command? */
93 if (d->init_state)
94 fatal("[ 8259: WARNING: Was in init-state, but"
95 " it was aborted? ]\n");
96 d->init_state = 0;
97
98 if (idata == 0x0a) {
99 d->current_command = 0x0a;
100 } else if (idata == 0x0b) {
101 d->current_command = 0x0b;
102 } else if (idata == 0x0c) {
103 /* Put Master in Buffered Mode */
104 d->current_command = 0x0c;
105 } else if (idata == 0x20) {
106 int old_irr = d->irr;
107 /* End Of Interrupt */
108 /* TODO: in buffered mode, is this an EOI 0? */
109 d->irr &= ~d->isr;
110 d->isr = 0;
111 /* Recalculate interrupt assertions,
112 if necessary: */
113 if ((old_irr & ~d->ier) != (d->irr & ~d->ier))
114 cpu_interrupt(cpu, d->irq_nr);
115 } else if ((idata >= 0x21 && idata <= 0x27) ||
116 (idata >= 0x60 && idata <= 0x67) ||
117 (idata >= 0xe0 && idata <= 0xe7)) {
118 /* Specific EOI */
119 int old_irr = d->irr;
120 d->irr &= ~(1 << (idata & 7));
121 d->isr &= ~(1 << (idata & 7));
122 /* Recalc. int assertions, if necessary: */
123 if ((old_irr & ~d->ier) != (d->irr & ~d->ier))
124 cpu_interrupt(cpu, d->irq_nr);
125 } else if (idata == 0x68) {
126 /* Set Special Mask Mode */
127 /* TODO */
128 } else if (idata >= 0xc0 && idata <= 0xc7) {
129 /* Set IRQ Priority Order */
130 /* TODO */
131 } else {
132 fatal("[ 8259: unimplemented command 0x%02x"
133 " ]\n", (int)idata);
134 cpu->running = 0;
135 }
136 } else {
137 switch (d->current_command) {
138 case 0x0a:
139 odata = d->irr;
140 break;
141 case 0x0b:
142 odata = d->isr;
143 break;
144 case 0x0c:
145 /* Buffered mode. */
146 odata = 0x00;
147 for (i=0; i<8; i++)
148 if ((d->irr >> i) & 1) {
149 odata = 0x80 | i;
150 break;
151 }
152 break;
153 default:
154 odata = 0x00;
155 for (i=0; i<8; i++)
156 if ((d->irr >> i) & 1) {
157 odata = 0x80 | i;
158 break;
159 }
160 break;
161 /*
162 * TODO: The "default" label should really do
163 * something like this:
164 *
165 * fatal("[ 8259: unimplemented command 0x%02x"
166 * " while reading ]\n", d->current_command);
167 * cpu->running = 0;
168 *
169 * but Linux seems to read from the secondary PIC
170 * in a manner which works better the way things
171 * are coded right now.
172 */
173 }
174 }
175 break;
176 case 0x01:
177 if (d->init_state > 0) {
178 if (d->init_state == 1) {
179 d->irq_base = idata & 0xf8;
180 /* This happens on non-x86 machines:
181 if (idata & 7)
182 fatal("[ 8259: WARNING! Lowest"
183 " bits in Init Cmd 1 are"
184 " non-zero! ]\n"); */
185 d->init_state = 2;
186 } else if (d->init_state == 2) {
187 /* Slave attachment. TODO */
188 d->init_state = 3;
189 } else if (d->init_state == 3) {
190 if (idata & 0x02) {
191 /* Should not be set in PCs, but
192 on CATS, for example, it is set. */
193 debug("[ 8259: WARNING! Bit 1 i"
194 "n Init Cmd 4 is set! ]\n");
195 }
196 if (!(idata & 0x01))
197 fatal("[ 8259: WARNING! Bit 0 "
198 "in Init Cmd 4 is not"
199 " set! ]\n");
200 d->init_state = 0;
201 }
202 break;
203 }
204
205 if (writeflag == MEM_WRITE) {
206 int old_ier = d->ier;
207 d->ier = idata;
208
209 /* Recalculate interrupt assertions,
210 if necessary: */
211 if ((d->irr & ~old_ier) != (d->irr & ~d->ier))
212 cpu_interrupt(cpu, d->irq_nr);
213 } else {
214 odata = d->ier;
215 }
216 break;
217 default:
218 if (writeflag == MEM_WRITE) {
219 fatal("[ 8259: unimplemented write to address 0x%x"
220 " data=0x%02x ]\n", (int)relative_addr, (int)idata);
221 cpu->running = 0;
222 } else {
223 fatal("[ 8259: unimplemented read from address 0x%x "
224 "]\n", (int)relative_addr);
225 cpu->running = 0;
226 }
227 }
228
229 if (writeflag == MEM_READ)
230 memory_writemax64(cpu, data, len, odata);
231
232 return 1;
233 }
234
235
236 /*
237 * devinit_8259():
238 *
239 * Initialize an 8259 PIC. Important notes:
240 *
241 * x) Most systems use _TWO_ 8259 PICs. These should be registered
242 * as separate devices.
243 *
244 * x) The irq number specified is the number used to re-calculate
245 * CPU interrupt assertions. It is _not_ the irq number at
246 * which the PIC is connected. (That is left to machine specific
247 * code in src/machine.c.)
248 */
249 DEVINIT(8259)
250 {
251 struct pic8259_data *d = malloc(sizeof(struct pic8259_data));
252 char *name2;
253 size_t nlen = strlen(devinit->name) + 20;
254
255 if (d == NULL) {
256 fprintf(stderr, "out of memory\n");
257 exit(1);
258 }
259 memset(d, 0, sizeof(struct pic8259_data));
260 d->irq_nr = devinit->irq_nr;
261
262 name2 = malloc(nlen);
263 snprintf(name2, nlen, "%s", devinit->name);
264 if ((devinit->addr & 0xfff) == 0xa0) {
265 strlcat(name2, " [secondary]", nlen);
266 d->irq_base = 8;
267 }
268
269 memory_device_register(devinit->machine->memory, name2,
270 devinit->addr, DEV_8259_LENGTH, dev_8259_access, d,
271 DM_DEFAULT, NULL);
272
273 devinit->return_ptr = d;
274 return 1;
275 }
276

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