25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_8259.c,v 1.15 2005/10/26 14:37:03 debug Exp $ |
* $Id: dev_8259.c,v 1.22 2005/11/23 18:16:42 debug Exp $ |
29 |
* |
* |
30 |
* 8259 Programmable Interrupt Controller. |
* 8259 Programmable Interrupt Controller. |
31 |
* |
* |
100 |
" it was aborted? ]\n"); |
" it was aborted? ]\n"); |
101 |
d->init_state = 0; |
d->init_state = 0; |
102 |
|
|
103 |
switch (idata) { |
if (idata == 0x0a) { |
|
case 0x0a: |
|
104 |
d->current_command = 0x0a; |
d->current_command = 0x0a; |
105 |
break; |
} else if (idata == 0x0b) { |
|
case 0x0b: |
|
106 |
d->current_command = 0x0b; |
d->current_command = 0x0b; |
107 |
break; |
} else if (idata == 0x0c) { |
|
case 0x0c: |
|
108 |
/* Put Master in Buffered Mode */ |
/* Put Master in Buffered Mode */ |
109 |
d->current_command = 0x0c; |
d->current_command = 0x0c; |
110 |
break; |
} else if (idata == 0x20) { |
111 |
case 0x20: /* End Of Interrupt */ |
int old_irr = d->irr; |
112 |
/* |
/* End Of Interrupt */ |
113 |
* TODO: in buffered mode, is this an EOI 0? |
/* TODO: in buffered mode, is this an EOI 0? */ |
|
*/ |
|
114 |
d->irr &= ~d->isr; |
d->irr &= ~d->isr; |
115 |
d->isr = 0; |
d->isr = 0; |
116 |
/* Recalculate interrupt assertions: */ |
/* Recalculate interrupt assertions, |
117 |
cpu_interrupt(cpu, d->irq_nr); |
if necessary: */ |
118 |
break; |
if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) |
119 |
case 0x21: /* Specific EOI */ |
cpu_interrupt(cpu, d->irq_nr); |
120 |
case 0x22: |
} else if ((idata >= 0x21 && idata <= 0x27) || |
121 |
case 0x23: |
(idata >= 0x60 && idata <= 0x67) || |
122 |
case 0x24: |
(idata >= 0xe0 && idata <= 0xe7)) { |
123 |
case 0x25: |
/* Specific EOI */ |
124 |
case 0x26: |
int old_irr = d->irr; |
|
case 0x27: |
|
|
case 0x60: |
|
|
case 0x61: |
|
|
case 0x62: |
|
|
case 0x63: |
|
|
case 0x64: |
|
|
case 0x65: |
|
|
case 0x66: |
|
|
case 0x67: /* Specific EOI */ |
|
125 |
d->irr &= ~(1 << (idata & 7)); |
d->irr &= ~(1 << (idata & 7)); |
126 |
d->isr &= ~(1 << (idata & 7)); |
d->isr &= ~(1 << (idata & 7)); |
127 |
/* Recalculate interrupt assertions: */ |
/* Recalc. int assertions, if necessary: */ |
128 |
cpu_interrupt(cpu, d->irq_nr); |
if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) |
129 |
break; |
cpu_interrupt(cpu, d->irq_nr); |
130 |
case 0x68: /* Set Special Mask Mode */ |
} else if (idata == 0x68) { |
131 |
|
/* Set Special Mask Mode */ |
132 |
/* TODO */ |
/* TODO */ |
133 |
break; |
} else if (idata >= 0xc0 && idata <= 0xc7) { |
134 |
case 0xc0: |
/* Set IRQ Priority Order */ |
|
case 0xc1: |
|
|
case 0xc2: |
|
|
case 0xc3: |
|
|
case 0xc4: |
|
|
case 0xc5: |
|
|
case 0xc6: |
|
|
case 0xc7: /* Set IRQ Priority Order */ |
|
135 |
/* TODO */ |
/* TODO */ |
136 |
break; |
} else { |
|
default: |
|
137 |
fatal("[ 8259: unimplemented command 0x%02x" |
fatal("[ 8259: unimplemented command 0x%02x" |
138 |
" ]\n", idata); |
" ]\n", (int)idata); |
139 |
cpu->running = 0; |
cpu->running = 0; |
140 |
} |
} |
141 |
} else { |
} else { |
148 |
break; |
break; |
149 |
case 0x0c: |
case 0x0c: |
150 |
/* Buffered mode. */ |
/* Buffered mode. */ |
151 |
|
odata = 0x00; |
152 |
|
for (i=0; i<8; i++) |
153 |
|
if ((d->irr >> i) & 1) { |
154 |
|
odata = 0x80 | i; |
155 |
|
break; |
156 |
|
} |
157 |
|
break; |
158 |
default: |
default: |
159 |
odata = 0x00; |
odata = 0x00; |
160 |
for (i=0; i<8; i++) |
for (i=0; i<8; i++) |
192 |
/* Slave attachment. TODO */ |
/* Slave attachment. TODO */ |
193 |
d->init_state = 3; |
d->init_state = 3; |
194 |
} else if (d->init_state == 3) { |
} else if (d->init_state == 3) { |
195 |
if (idata & 0x02) |
if (idata & 0x02) { |
196 |
fatal("[ 8259: WARNING! Bit 1 i" |
/* Should not be set in PCs, but |
197 |
|
on CATS, for example, it is set. */ |
198 |
|
debug("[ 8259: WARNING! Bit 1 i" |
199 |
"n Init Cmd 4 is set! ]\n"); |
"n Init Cmd 4 is set! ]\n"); |
200 |
|
} |
201 |
if (!(idata & 0x01)) |
if (!(idata & 0x01)) |
202 |
fatal("[ 8259: WARNING! Bit 0 " |
fatal("[ 8259: WARNING! Bit 0 " |
203 |
"in Init Cmd 4 is not" |
"in Init Cmd 4 is not" |
208 |
} |
} |
209 |
|
|
210 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
211 |
|
int old_ier = d->ier; |
212 |
d->ier = idata; |
d->ier = idata; |
213 |
/* Recalculate interrupt assertions: */ |
|
214 |
cpu_interrupt(cpu, d->irq_nr); |
/* Recalculate interrupt assertions, |
215 |
|
if necessary: */ |
216 |
|
if ((d->irr & ~old_ier) != (d->irr & ~d->ier)) |
217 |
|
cpu_interrupt(cpu, d->irq_nr); |
218 |
} else { |
} else { |
219 |
odata = d->ier; |
odata = d->ier; |
220 |
} |
} |
273 |
|
|
274 |
memory_device_register(devinit->machine->memory, name2, |
memory_device_register(devinit->machine->memory, name2, |
275 |
devinit->addr, DEV_8259_LENGTH, dev_8259_access, d, |
devinit->addr, DEV_8259_LENGTH, dev_8259_access, d, |
276 |
MEM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
277 |
|
|
278 |
devinit->return_ptr = d; |
devinit->return_ptr = d; |
279 |
return 1; |
return 1; |