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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_8259.c,v 1.14 2005/08/05 09:08:20 debug Exp $ |
* $Id: dev_8259.c,v 1.25 2006/07/21 16:55:41 debug Exp $ |
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* |
* |
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* 8259 Programmable Interrupt Controller. |
* 8259 Programmable Interrupt Controller. |
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* |
* |
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/* #define DEV_8259_DEBUG */ |
/* #define DEV_8259_DEBUG */ |
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/* |
DEVICE_ACCESS(8259) |
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* dev_8259_access(): |
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*/ |
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int dev_8259_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
{ |
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struct pic8259_data *d = (struct pic8259_data *) extra; |
struct pic8259_data *d = (struct pic8259_data *) extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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int i; |
int i; |
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idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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#ifdef DEV_8259_DEBUG |
#ifdef DEV_8259_DEBUG |
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if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
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" it was aborted? ]\n"); |
" it was aborted? ]\n"); |
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d->init_state = 0; |
d->init_state = 0; |
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switch (idata) { |
if (idata == 0x0a) { |
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case 0x0a: |
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d->current_command = 0x0a; |
d->current_command = 0x0a; |
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break; |
} else if (idata == 0x0b) { |
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case 0x0b: |
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d->current_command = 0x0b; |
d->current_command = 0x0b; |
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break; |
} else if (idata == 0x0c) { |
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case 0x0c: |
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/* Put Master in Buffered Mode */ |
/* Put Master in Buffered Mode */ |
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d->current_command = 0x0c; |
d->current_command = 0x0c; |
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break; |
} else if (idata == 0x20) { |
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case 0x20: /* End Of Interrupt */ |
int old_irr = d->irr; |
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/* |
/* End Of Interrupt */ |
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* TODO: in buffered mode, is this an EOI 0? |
/* TODO: in buffered mode, is this an EOI 0? */ |
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*/ |
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d->irr &= ~d->isr; |
d->irr &= ~d->isr; |
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d->isr = 0; |
d->isr = 0; |
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/* Recalculate interrupt assertions: */ |
/* Recalculate interrupt assertions, |
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cpu_interrupt(cpu, d->irq_nr); |
if necessary: */ |
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break; |
if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) |
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case 0x21: /* Specific EOI */ |
cpu_interrupt(cpu, d->irq_nr); |
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case 0x22: |
} else if ((idata >= 0x21 && idata <= 0x27) || |
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case 0x23: |
(idata >= 0x60 && idata <= 0x67) || |
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case 0x24: |
(idata >= 0xe0 && idata <= 0xe7)) { |
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case 0x25: |
/* Specific EOI */ |
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case 0x26: |
int old_irr = d->irr; |
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case 0x27: |
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case 0x60: |
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case 0x61: |
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case 0x62: |
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case 0x63: |
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case 0x64: |
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case 0x65: |
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case 0x66: |
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case 0x67: /* Specific EOI */ |
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d->irr &= ~(1 << (idata & 7)); |
d->irr &= ~(1 << (idata & 7)); |
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d->isr &= ~(1 << (idata & 7)); |
d->isr &= ~(1 << (idata & 7)); |
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/* Recalculate interrupt assertions: */ |
/* Recalc. int assertions, if necessary: */ |
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cpu_interrupt(cpu, d->irq_nr); |
if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) |
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break; |
cpu_interrupt(cpu, d->irq_nr); |
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case 0x68: /* Set Special Mask Mode */ |
} else if (idata == 0x68) { |
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/* Set Special Mask Mode */ |
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/* TODO */ |
/* TODO */ |
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break; |
} else if (idata >= 0xc0 && idata <= 0xc7) { |
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case 0xc0: |
/* Set IRQ Priority Order */ |
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case 0xc1: |
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case 0xc2: |
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case 0xc3: |
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case 0xc4: |
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case 0xc5: |
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case 0xc6: |
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case 0xc7: /* Set IRQ Priority Order */ |
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/* TODO */ |
/* TODO */ |
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break; |
} else { |
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default: |
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fatal("[ 8259: unimplemented command 0x%02x" |
fatal("[ 8259: unimplemented command 0x%02x" |
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" ]\n", idata); |
" ]\n", (int)idata); |
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cpu->running = 0; |
cpu->running = 0; |
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} |
} |
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} else { |
} else { |
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break; |
break; |
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case 0x0c: |
case 0x0c: |
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/* Buffered mode. */ |
/* Buffered mode. */ |
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odata = 0x00; |
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for (i=0; i<8; i++) |
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if ((d->irr >> i) & 1) { |
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odata = 0x80 | i; |
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break; |
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} |
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break; |
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default: |
default: |
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odata = 0x00; |
odata = 0x00; |
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for (i=0; i<8; i++) |
for (i=0; i<8; i++) |
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/* Slave attachment. TODO */ |
/* Slave attachment. TODO */ |
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d->init_state = 3; |
d->init_state = 3; |
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} else if (d->init_state == 3) { |
} else if (d->init_state == 3) { |
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if (idata & 0x02) |
if (idata & 0x02) { |
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fatal("[ 8259: WARNING! Bit 1 i" |
/* Should not be set in PCs, but |
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on CATS, for example, it is set. */ |
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debug("[ 8259: WARNING! Bit 1 i" |
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"n Init Cmd 4 is set! ]\n"); |
"n Init Cmd 4 is set! ]\n"); |
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} |
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if (!(idata & 0x01)) |
if (!(idata & 0x01)) |
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fatal("[ 8259: WARNING! Bit 0 " |
fatal("[ 8259: WARNING! Bit 0 " |
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"in Init Cmd 4 is not" |
"in Init Cmd 4 is not" |
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} |
} |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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int old_ier = d->ier; |
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d->ier = idata; |
d->ier = idata; |
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/* Recalculate interrupt assertions: */ |
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cpu_interrupt(cpu, d->irq_nr); |
/* Recalculate interrupt assertions, |
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if necessary: */ |
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if ((d->irr & ~old_ier) != (d->irr & ~d->ier)) |
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cpu_interrupt(cpu, d->irq_nr); |
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} else { |
} else { |
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odata = d->ier; |
odata = d->ier; |
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} |
} |
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* which the PIC is connected. (That is left to machine specific |
* which the PIC is connected. (That is left to machine specific |
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* code in src/machine.c.) |
* code in src/machine.c.) |
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*/ |
*/ |
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int devinit_8259(struct devinit *devinit) |
DEVINIT(8259) |
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{ |
{ |
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struct pic8259_data *d = malloc(sizeof(struct pic8259_data)); |
struct pic8259_data *d = malloc(sizeof(struct pic8259_data)); |
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char *name2; |
char *name2; |
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memory_device_register(devinit->machine->memory, name2, |
memory_device_register(devinit->machine->memory, name2, |
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devinit->addr, DEV_8259_LENGTH, dev_8259_access, d, |
devinit->addr, DEV_8259_LENGTH, dev_8259_access, d, |
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MEM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
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devinit->return_ptr = d; |
devinit->return_ptr = d; |
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return 1; |
return 1; |