/[gxemul]/trunk/src/devices/dev_8259.c
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Annotation of /trunk/src/devices/dev_8259.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 7945 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 dpavlin 6 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 6 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: dev_8259.c,v 1.30 2007/06/15 18:13:04 debug Exp $
29 dpavlin 6 *
30 dpavlin 42 * COMMENT: Intel 8259 Programmable Interrupt Controller
31 dpavlin 6 *
32 dpavlin 12 * See the following URL for more details:
33 dpavlin 6 * http://www.nondot.org/sabre/os/files/MiscHW/8259pic.txt
34     */
35    
36     #include <stdio.h>
37     #include <stdlib.h>
38     #include <string.h>
39    
40     #include "cpu.h"
41     #include "device.h"
42     #include "devices.h"
43     #include "emul.h"
44     #include "machine.h"
45     #include "memory.h"
46     #include "misc.h"
47    
48    
49     #define DEV_8259_LENGTH 2
50    
51 dpavlin 12 /* #define DEV_8259_DEBUG */
52 dpavlin 6
53 dpavlin 12
54 dpavlin 22 DEVICE_ACCESS(8259)
55 dpavlin 6 {
56 dpavlin 42 struct pic8259_data *d = extra;
57 dpavlin 6 uint64_t idata = 0, odata = 0;
58 dpavlin 12 int i;
59 dpavlin 6
60 dpavlin 18 if (writeflag == MEM_WRITE)
61     idata = memory_readmax64(cpu, data, len);
62 dpavlin 6
63 dpavlin 12 #ifdef DEV_8259_DEBUG
64     if (writeflag == MEM_READ)
65     fatal("[ 8259: read from 0x%x ]\n", (int)relative_addr);
66     else
67     fatal("[ 8259: write to 0x%x: 0x%x ]\n",
68     (int)relative_addr, (int)idata);
69     #endif
70    
71 dpavlin 6 switch (relative_addr) {
72     case 0x00:
73     if (writeflag == MEM_WRITE) {
74     if ((idata & 0x10) == 0x10) {
75     /* Bit 3: 0=edge, 1=level */
76     if (idata & 0x08)
77     fatal("[ 8259: TODO: Level "
78     "triggered (MCA bus) ]\n");
79     if (idata & 0x04)
80     fatal("[ 8259: WARNING: Bit 2 set ]\n");
81     /* Bit 1: 0=cascade, 1=single */
82     /* Bit 0: 1=4th init byte */
83 dpavlin 12 /* This happens on non-x86 systems:
84     if (!(idata & 0x01))
85 dpavlin 6 fatal("[ 8259: WARNING: Bit 0 NOT set!"
86 dpavlin 12 "!! ]\n"); */
87 dpavlin 6 d->init_state = 1;
88     break;
89     }
90    
91     /* TODO: Is it ok to abort init state when there
92     is a non-init command? */
93     if (d->init_state)
94     fatal("[ 8259: WARNING: Was in init-state, but"
95     " it was aborted? ]\n");
96     d->init_state = 0;
97    
98 dpavlin 20 if (idata == 0x0a) {
99 dpavlin 6 d->current_command = 0x0a;
100 dpavlin 20 } else if (idata == 0x0b) {
101 dpavlin 6 d->current_command = 0x0b;
102 dpavlin 20 } else if (idata == 0x0c) {
103 dpavlin 12 /* Put Master in Buffered Mode */
104     d->current_command = 0x0c;
105 dpavlin 20 } else if (idata == 0x20) {
106     int old_irr = d->irr;
107     /* End Of Interrupt */
108     /* TODO: in buffered mode, is this an EOI 0? */
109 dpavlin 6 d->irr &= ~d->isr;
110     d->isr = 0;
111 dpavlin 20 /* Recalculate interrupt assertions,
112     if necessary: */
113 dpavlin 34 if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) {
114     if (d->irr & ~d->ier)
115     INTERRUPT_ASSERT(d->irq);
116     else
117     INTERRUPT_DEASSERT(d->irq);
118     }
119 dpavlin 20 } else if ((idata >= 0x21 && idata <= 0x27) ||
120     (idata >= 0x60 && idata <= 0x67) ||
121     (idata >= 0xe0 && idata <= 0xe7)) {
122     /* Specific EOI */
123     int old_irr = d->irr;
124 dpavlin 6 d->irr &= ~(1 << (idata & 7));
125     d->isr &= ~(1 << (idata & 7));
126 dpavlin 20 /* Recalc. int assertions, if necessary: */
127 dpavlin 34 if ((old_irr & ~d->ier) != (d->irr & ~d->ier)) {
128     if (d->irr & ~d->ier)
129     INTERRUPT_ASSERT(d->irq);
130     else
131     INTERRUPT_DEASSERT(d->irq);
132     }
133 dpavlin 20 } else if (idata == 0x68) {
134     /* Set Special Mask Mode */
135 dpavlin 6 /* TODO */
136 dpavlin 20 } else if (idata >= 0xc0 && idata <= 0xc7) {
137     /* Set IRQ Priority Order */
138 dpavlin 6 /* TODO */
139 dpavlin 20 } else {
140 dpavlin 6 fatal("[ 8259: unimplemented command 0x%02x"
141 dpavlin 20 " ]\n", (int)idata);
142 dpavlin 6 cpu->running = 0;
143     }
144     } else {
145     switch (d->current_command) {
146     case 0x0a:
147     odata = d->irr;
148     break;
149     case 0x0b:
150     odata = d->isr;
151     break;
152 dpavlin 12 case 0x0c:
153     /* Buffered mode. */
154 dpavlin 20 odata = 0x00;
155     for (i=0; i<8; i++)
156     if ((d->irr >> i) & 1) {
157     odata = 0x80 | i;
158     break;
159     }
160     break;
161 dpavlin 6 default:
162 dpavlin 12 odata = 0x00;
163     for (i=0; i<8; i++)
164     if ((d->irr >> i) & 1) {
165     odata = 0x80 | i;
166     break;
167     }
168     break;
169     /*
170     * TODO: The "default" label should really do
171     * something like this:
172     *
173     * fatal("[ 8259: unimplemented command 0x%02x"
174     * " while reading ]\n", d->current_command);
175     * cpu->running = 0;
176     *
177     * but Linux seems to read from the secondary PIC
178     * in a manner which works better the way things
179     * are coded right now.
180     */
181 dpavlin 6 }
182     }
183     break;
184     case 0x01:
185     if (d->init_state > 0) {
186     if (d->init_state == 1) {
187     d->irq_base = idata & 0xf8;
188 dpavlin 12 /* This happens on non-x86 machines:
189     if (idata & 7)
190 dpavlin 6 fatal("[ 8259: WARNING! Lowest"
191     " bits in Init Cmd 1 are"
192 dpavlin 12 " non-zero! ]\n"); */
193 dpavlin 6 d->init_state = 2;
194     } else if (d->init_state == 2) {
195     /* Slave attachment. TODO */
196     d->init_state = 3;
197     } else if (d->init_state == 3) {
198 dpavlin 20 if (idata & 0x02) {
199     /* Should not be set in PCs, but
200     on CATS, for example, it is set. */
201     debug("[ 8259: WARNING! Bit 1 i"
202 dpavlin 6 "n Init Cmd 4 is set! ]\n");
203 dpavlin 20 }
204 dpavlin 6 if (!(idata & 0x01))
205     fatal("[ 8259: WARNING! Bit 0 "
206     "in Init Cmd 4 is not"
207     " set! ]\n");
208     d->init_state = 0;
209     }
210     break;
211     }
212    
213     if (writeflag == MEM_WRITE) {
214 dpavlin 20 int old_ier = d->ier;
215 dpavlin 6 d->ier = idata;
216 dpavlin 20
217     /* Recalculate interrupt assertions,
218     if necessary: */
219 dpavlin 34 if ((d->irr & ~old_ier) != (d->irr & ~d->ier)) {
220     if (d->irr & ~d->ier)
221     INTERRUPT_ASSERT(d->irq);
222     else
223     INTERRUPT_DEASSERT(d->irq);
224     }
225 dpavlin 6 } else {
226     odata = d->ier;
227     }
228     break;
229     default:
230     if (writeflag == MEM_WRITE) {
231     fatal("[ 8259: unimplemented write to address 0x%x"
232     " data=0x%02x ]\n", (int)relative_addr, (int)idata);
233     cpu->running = 0;
234     } else {
235     fatal("[ 8259: unimplemented read from address 0x%x "
236     "]\n", (int)relative_addr);
237     cpu->running = 0;
238     }
239     }
240    
241     if (writeflag == MEM_READ)
242     memory_writemax64(cpu, data, len, odata);
243    
244     return 1;
245     }
246    
247    
248     /*
249     * devinit_8259():
250 dpavlin 12 *
251     * Initialize an 8259 PIC. Important notes:
252     *
253     * x) Most systems use _TWO_ 8259 PICs. These should be registered
254     * as separate devices.
255     *
256     * x) The irq number specified is the number used to re-calculate
257     * CPU interrupt assertions. It is _not_ the irq number at
258     * which the PIC is connected. (That is left to machine specific
259     * code in src/machine.c.)
260 dpavlin 6 */
261 dpavlin 22 DEVINIT(8259)
262 dpavlin 6 {
263 dpavlin 42 struct pic8259_data *d;
264 dpavlin 6 char *name2;
265 dpavlin 12 size_t nlen = strlen(devinit->name) + 20;
266 dpavlin 6
267 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct pic8259_data)));
268 dpavlin 6 memset(d, 0, sizeof(struct pic8259_data));
269    
270 dpavlin 34 INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
271    
272 dpavlin 42 CHECK_ALLOCATION(name2 = malloc(nlen));
273 dpavlin 6 snprintf(name2, nlen, "%s", devinit->name);
274 dpavlin 12 if ((devinit->addr & 0xfff) == 0xa0) {
275 dpavlin 10 strlcat(name2, " [secondary]", nlen);
276 dpavlin 12 d->irq_base = 8;
277     }
278 dpavlin 6
279     memory_device_register(devinit->machine->memory, name2,
280 dpavlin 12 devinit->addr, DEV_8259_LENGTH, dev_8259_access, d,
281 dpavlin 20 DM_DEFAULT, NULL);
282 dpavlin 6
283     devinit->return_ptr = d;
284     return 1;
285     }
286    

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