/[gxemul]/trunk/src/devices/dev_8259.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Annotation of /trunk/src/devices/dev_8259.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 22 - (hide annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 7770 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 6 /*
2 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 dpavlin 6 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 22 * $Id: dev_8259.c,v 1.24 2006/02/09 20:02:58 debug Exp $
29 dpavlin 6 *
30     * 8259 Programmable Interrupt Controller.
31     *
32 dpavlin 12 * See the following URL for more details:
33 dpavlin 6 * http://www.nondot.org/sabre/os/files/MiscHW/8259pic.txt
34     */
35    
36     #include <stdio.h>
37     #include <stdlib.h>
38     #include <string.h>
39    
40     #include "cpu.h"
41     #include "device.h"
42     #include "devices.h"
43     #include "emul.h"
44     #include "machine.h"
45     #include "memory.h"
46     #include "misc.h"
47    
48    
49     #define DEV_8259_LENGTH 2
50    
51 dpavlin 12 /* #define DEV_8259_DEBUG */
52 dpavlin 6
53 dpavlin 12
54 dpavlin 6 /*
55     * dev_8259_access():
56     */
57 dpavlin 22 DEVICE_ACCESS(8259)
58 dpavlin 6 {
59     struct pic8259_data *d = (struct pic8259_data *) extra;
60     uint64_t idata = 0, odata = 0;
61 dpavlin 12 int i;
62 dpavlin 6
63 dpavlin 18 if (writeflag == MEM_WRITE)
64     idata = memory_readmax64(cpu, data, len);
65 dpavlin 6
66 dpavlin 12 #ifdef DEV_8259_DEBUG
67     if (writeflag == MEM_READ)
68     fatal("[ 8259: read from 0x%x ]\n", (int)relative_addr);
69     else
70     fatal("[ 8259: write to 0x%x: 0x%x ]\n",
71     (int)relative_addr, (int)idata);
72     #endif
73    
74 dpavlin 6 switch (relative_addr) {
75     case 0x00:
76     if (writeflag == MEM_WRITE) {
77     if ((idata & 0x10) == 0x10) {
78     /* Bit 3: 0=edge, 1=level */
79     if (idata & 0x08)
80     fatal("[ 8259: TODO: Level "
81     "triggered (MCA bus) ]\n");
82     if (idata & 0x04)
83     fatal("[ 8259: WARNING: Bit 2 set ]\n");
84     /* Bit 1: 0=cascade, 1=single */
85     /* Bit 0: 1=4th init byte */
86 dpavlin 12 /* This happens on non-x86 systems:
87     if (!(idata & 0x01))
88 dpavlin 6 fatal("[ 8259: WARNING: Bit 0 NOT set!"
89 dpavlin 12 "!! ]\n"); */
90 dpavlin 6 d->init_state = 1;
91     break;
92     }
93    
94     /* TODO: Is it ok to abort init state when there
95     is a non-init command? */
96     if (d->init_state)
97     fatal("[ 8259: WARNING: Was in init-state, but"
98     " it was aborted? ]\n");
99     d->init_state = 0;
100    
101 dpavlin 20 if (idata == 0x0a) {
102 dpavlin 6 d->current_command = 0x0a;
103 dpavlin 20 } else if (idata == 0x0b) {
104 dpavlin 6 d->current_command = 0x0b;
105 dpavlin 20 } else if (idata == 0x0c) {
106 dpavlin 12 /* Put Master in Buffered Mode */
107     d->current_command = 0x0c;
108 dpavlin 20 } else if (idata == 0x20) {
109     int old_irr = d->irr;
110     /* End Of Interrupt */
111     /* TODO: in buffered mode, is this an EOI 0? */
112 dpavlin 6 d->irr &= ~d->isr;
113     d->isr = 0;
114 dpavlin 20 /* Recalculate interrupt assertions,
115     if necessary: */
116     if ((old_irr & ~d->ier) != (d->irr & ~d->ier))
117     cpu_interrupt(cpu, d->irq_nr);
118     } else if ((idata >= 0x21 && idata <= 0x27) ||
119     (idata >= 0x60 && idata <= 0x67) ||
120     (idata >= 0xe0 && idata <= 0xe7)) {
121     /* Specific EOI */
122     int old_irr = d->irr;
123 dpavlin 6 d->irr &= ~(1 << (idata & 7));
124     d->isr &= ~(1 << (idata & 7));
125 dpavlin 20 /* Recalc. int assertions, if necessary: */
126     if ((old_irr & ~d->ier) != (d->irr & ~d->ier))
127     cpu_interrupt(cpu, d->irq_nr);
128     } else if (idata == 0x68) {
129     /* Set Special Mask Mode */
130 dpavlin 6 /* TODO */
131 dpavlin 20 } else if (idata >= 0xc0 && idata <= 0xc7) {
132     /* Set IRQ Priority Order */
133 dpavlin 6 /* TODO */
134 dpavlin 20 } else {
135 dpavlin 6 fatal("[ 8259: unimplemented command 0x%02x"
136 dpavlin 20 " ]\n", (int)idata);
137 dpavlin 6 cpu->running = 0;
138     }
139     } else {
140     switch (d->current_command) {
141     case 0x0a:
142     odata = d->irr;
143     break;
144     case 0x0b:
145     odata = d->isr;
146     break;
147 dpavlin 12 case 0x0c:
148     /* Buffered mode. */
149 dpavlin 20 odata = 0x00;
150     for (i=0; i<8; i++)
151     if ((d->irr >> i) & 1) {
152     odata = 0x80 | i;
153     break;
154     }
155     break;
156 dpavlin 6 default:
157 dpavlin 12 odata = 0x00;
158     for (i=0; i<8; i++)
159     if ((d->irr >> i) & 1) {
160     odata = 0x80 | i;
161     break;
162     }
163     break;
164     /*
165     * TODO: The "default" label should really do
166     * something like this:
167     *
168     * fatal("[ 8259: unimplemented command 0x%02x"
169     * " while reading ]\n", d->current_command);
170     * cpu->running = 0;
171     *
172     * but Linux seems to read from the secondary PIC
173     * in a manner which works better the way things
174     * are coded right now.
175     */
176 dpavlin 6 }
177     }
178     break;
179     case 0x01:
180     if (d->init_state > 0) {
181     if (d->init_state == 1) {
182     d->irq_base = idata & 0xf8;
183 dpavlin 12 /* This happens on non-x86 machines:
184     if (idata & 7)
185 dpavlin 6 fatal("[ 8259: WARNING! Lowest"
186     " bits in Init Cmd 1 are"
187 dpavlin 12 " non-zero! ]\n"); */
188 dpavlin 6 d->init_state = 2;
189     } else if (d->init_state == 2) {
190     /* Slave attachment. TODO */
191     d->init_state = 3;
192     } else if (d->init_state == 3) {
193 dpavlin 20 if (idata & 0x02) {
194     /* Should not be set in PCs, but
195     on CATS, for example, it is set. */
196     debug("[ 8259: WARNING! Bit 1 i"
197 dpavlin 6 "n Init Cmd 4 is set! ]\n");
198 dpavlin 20 }
199 dpavlin 6 if (!(idata & 0x01))
200     fatal("[ 8259: WARNING! Bit 0 "
201     "in Init Cmd 4 is not"
202     " set! ]\n");
203     d->init_state = 0;
204     }
205     break;
206     }
207    
208     if (writeflag == MEM_WRITE) {
209 dpavlin 20 int old_ier = d->ier;
210 dpavlin 6 d->ier = idata;
211 dpavlin 20
212     /* Recalculate interrupt assertions,
213     if necessary: */
214     if ((d->irr & ~old_ier) != (d->irr & ~d->ier))
215     cpu_interrupt(cpu, d->irq_nr);
216 dpavlin 6 } else {
217     odata = d->ier;
218     }
219     break;
220     default:
221     if (writeflag == MEM_WRITE) {
222     fatal("[ 8259: unimplemented write to address 0x%x"
223     " data=0x%02x ]\n", (int)relative_addr, (int)idata);
224     cpu->running = 0;
225     } else {
226     fatal("[ 8259: unimplemented read from address 0x%x "
227     "]\n", (int)relative_addr);
228     cpu->running = 0;
229     }
230     }
231    
232     if (writeflag == MEM_READ)
233     memory_writemax64(cpu, data, len, odata);
234    
235     return 1;
236     }
237    
238    
239     /*
240     * devinit_8259():
241 dpavlin 12 *
242     * Initialize an 8259 PIC. Important notes:
243     *
244     * x) Most systems use _TWO_ 8259 PICs. These should be registered
245     * as separate devices.
246     *
247     * x) The irq number specified is the number used to re-calculate
248     * CPU interrupt assertions. It is _not_ the irq number at
249     * which the PIC is connected. (That is left to machine specific
250     * code in src/machine.c.)
251 dpavlin 6 */
252 dpavlin 22 DEVINIT(8259)
253 dpavlin 6 {
254     struct pic8259_data *d = malloc(sizeof(struct pic8259_data));
255     char *name2;
256 dpavlin 12 size_t nlen = strlen(devinit->name) + 20;
257 dpavlin 6
258     if (d == NULL) {
259     fprintf(stderr, "out of memory\n");
260     exit(1);
261     }
262     memset(d, 0, sizeof(struct pic8259_data));
263     d->irq_nr = devinit->irq_nr;
264    
265     name2 = malloc(nlen);
266     snprintf(name2, nlen, "%s", devinit->name);
267 dpavlin 12 if ((devinit->addr & 0xfff) == 0xa0) {
268 dpavlin 10 strlcat(name2, " [secondary]", nlen);
269 dpavlin 12 d->irq_base = 8;
270     }
271 dpavlin 6
272     memory_device_register(devinit->machine->memory, name2,
273 dpavlin 12 devinit->addr, DEV_8259_LENGTH, dev_8259_access, d,
274 dpavlin 20 DM_DEFAULT, NULL);
275 dpavlin 6
276     devinit->return_ptr = d;
277     return 1;
278     }
279    

  ViewVC Help
Powered by ViewVC 1.1.26