/[gxemul]/trunk/src/devices/dev_8259.c
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Annotation of /trunk/src/devices/dev_8259.c

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Revision 20 - (hide annotations)
Mon Oct 8 16:19:23 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============


1 dpavlin 6 /*
2     * Copyright (C) 2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 20 * $Id: dev_8259.c,v 1.22 2005/11/23 18:16:42 debug Exp $
29 dpavlin 6 *
30     * 8259 Programmable Interrupt Controller.
31     *
32 dpavlin 12 * See the following URL for more details:
33 dpavlin 6 * http://www.nondot.org/sabre/os/files/MiscHW/8259pic.txt
34     */
35    
36     #include <stdio.h>
37     #include <stdlib.h>
38     #include <string.h>
39    
40     #include "cpu.h"
41     #include "device.h"
42     #include "devices.h"
43     #include "emul.h"
44     #include "machine.h"
45     #include "memory.h"
46     #include "misc.h"
47    
48    
49     #define DEV_8259_LENGTH 2
50    
51 dpavlin 12 /* #define DEV_8259_DEBUG */
52 dpavlin 6
53 dpavlin 12
54 dpavlin 6 /*
55     * dev_8259_access():
56     */
57     int dev_8259_access(struct cpu *cpu, struct memory *mem,
58     uint64_t relative_addr, unsigned char *data, size_t len,
59     int writeflag, void *extra)
60     {
61     struct pic8259_data *d = (struct pic8259_data *) extra;
62     uint64_t idata = 0, odata = 0;
63 dpavlin 12 int i;
64 dpavlin 6
65 dpavlin 18 if (writeflag == MEM_WRITE)
66     idata = memory_readmax64(cpu, data, len);
67 dpavlin 6
68 dpavlin 12 #ifdef DEV_8259_DEBUG
69     if (writeflag == MEM_READ)
70     fatal("[ 8259: read from 0x%x ]\n", (int)relative_addr);
71     else
72     fatal("[ 8259: write to 0x%x: 0x%x ]\n",
73     (int)relative_addr, (int)idata);
74     #endif
75    
76 dpavlin 6 switch (relative_addr) {
77     case 0x00:
78     if (writeflag == MEM_WRITE) {
79     if ((idata & 0x10) == 0x10) {
80     /* Bit 3: 0=edge, 1=level */
81     if (idata & 0x08)
82     fatal("[ 8259: TODO: Level "
83     "triggered (MCA bus) ]\n");
84     if (idata & 0x04)
85     fatal("[ 8259: WARNING: Bit 2 set ]\n");
86     /* Bit 1: 0=cascade, 1=single */
87     /* Bit 0: 1=4th init byte */
88 dpavlin 12 /* This happens on non-x86 systems:
89     if (!(idata & 0x01))
90 dpavlin 6 fatal("[ 8259: WARNING: Bit 0 NOT set!"
91 dpavlin 12 "!! ]\n"); */
92 dpavlin 6 d->init_state = 1;
93     break;
94     }
95    
96     /* TODO: Is it ok to abort init state when there
97     is a non-init command? */
98     if (d->init_state)
99     fatal("[ 8259: WARNING: Was in init-state, but"
100     " it was aborted? ]\n");
101     d->init_state = 0;
102    
103 dpavlin 20 if (idata == 0x0a) {
104 dpavlin 6 d->current_command = 0x0a;
105 dpavlin 20 } else if (idata == 0x0b) {
106 dpavlin 6 d->current_command = 0x0b;
107 dpavlin 20 } else if (idata == 0x0c) {
108 dpavlin 12 /* Put Master in Buffered Mode */
109     d->current_command = 0x0c;
110 dpavlin 20 } else if (idata == 0x20) {
111     int old_irr = d->irr;
112     /* End Of Interrupt */
113     /* TODO: in buffered mode, is this an EOI 0? */
114 dpavlin 6 d->irr &= ~d->isr;
115     d->isr = 0;
116 dpavlin 20 /* Recalculate interrupt assertions,
117     if necessary: */
118     if ((old_irr & ~d->ier) != (d->irr & ~d->ier))
119     cpu_interrupt(cpu, d->irq_nr);
120     } else if ((idata >= 0x21 && idata <= 0x27) ||
121     (idata >= 0x60 && idata <= 0x67) ||
122     (idata >= 0xe0 && idata <= 0xe7)) {
123     /* Specific EOI */
124     int old_irr = d->irr;
125 dpavlin 6 d->irr &= ~(1 << (idata & 7));
126     d->isr &= ~(1 << (idata & 7));
127 dpavlin 20 /* Recalc. int assertions, if necessary: */
128     if ((old_irr & ~d->ier) != (d->irr & ~d->ier))
129     cpu_interrupt(cpu, d->irq_nr);
130     } else if (idata == 0x68) {
131     /* Set Special Mask Mode */
132 dpavlin 6 /* TODO */
133 dpavlin 20 } else if (idata >= 0xc0 && idata <= 0xc7) {
134     /* Set IRQ Priority Order */
135 dpavlin 6 /* TODO */
136 dpavlin 20 } else {
137 dpavlin 6 fatal("[ 8259: unimplemented command 0x%02x"
138 dpavlin 20 " ]\n", (int)idata);
139 dpavlin 6 cpu->running = 0;
140     }
141     } else {
142     switch (d->current_command) {
143     case 0x0a:
144     odata = d->irr;
145     break;
146     case 0x0b:
147     odata = d->isr;
148     break;
149 dpavlin 12 case 0x0c:
150     /* Buffered mode. */
151 dpavlin 20 odata = 0x00;
152     for (i=0; i<8; i++)
153     if ((d->irr >> i) & 1) {
154     odata = 0x80 | i;
155     break;
156     }
157     break;
158 dpavlin 6 default:
159 dpavlin 12 odata = 0x00;
160     for (i=0; i<8; i++)
161     if ((d->irr >> i) & 1) {
162     odata = 0x80 | i;
163     break;
164     }
165     break;
166     /*
167     * TODO: The "default" label should really do
168     * something like this:
169     *
170     * fatal("[ 8259: unimplemented command 0x%02x"
171     * " while reading ]\n", d->current_command);
172     * cpu->running = 0;
173     *
174     * but Linux seems to read from the secondary PIC
175     * in a manner which works better the way things
176     * are coded right now.
177     */
178 dpavlin 6 }
179     }
180     break;
181     case 0x01:
182     if (d->init_state > 0) {
183     if (d->init_state == 1) {
184     d->irq_base = idata & 0xf8;
185 dpavlin 12 /* This happens on non-x86 machines:
186     if (idata & 7)
187 dpavlin 6 fatal("[ 8259: WARNING! Lowest"
188     " bits in Init Cmd 1 are"
189 dpavlin 12 " non-zero! ]\n"); */
190 dpavlin 6 d->init_state = 2;
191     } else if (d->init_state == 2) {
192     /* Slave attachment. TODO */
193     d->init_state = 3;
194     } else if (d->init_state == 3) {
195 dpavlin 20 if (idata & 0x02) {
196     /* Should not be set in PCs, but
197     on CATS, for example, it is set. */
198     debug("[ 8259: WARNING! Bit 1 i"
199 dpavlin 6 "n Init Cmd 4 is set! ]\n");
200 dpavlin 20 }
201 dpavlin 6 if (!(idata & 0x01))
202     fatal("[ 8259: WARNING! Bit 0 "
203     "in Init Cmd 4 is not"
204     " set! ]\n");
205     d->init_state = 0;
206     }
207     break;
208     }
209    
210     if (writeflag == MEM_WRITE) {
211 dpavlin 20 int old_ier = d->ier;
212 dpavlin 6 d->ier = idata;
213 dpavlin 20
214     /* Recalculate interrupt assertions,
215     if necessary: */
216     if ((d->irr & ~old_ier) != (d->irr & ~d->ier))
217     cpu_interrupt(cpu, d->irq_nr);
218 dpavlin 6 } else {
219     odata = d->ier;
220     }
221     break;
222     default:
223     if (writeflag == MEM_WRITE) {
224     fatal("[ 8259: unimplemented write to address 0x%x"
225     " data=0x%02x ]\n", (int)relative_addr, (int)idata);
226     cpu->running = 0;
227     } else {
228     fatal("[ 8259: unimplemented read from address 0x%x "
229     "]\n", (int)relative_addr);
230     cpu->running = 0;
231     }
232     }
233    
234     if (writeflag == MEM_READ)
235     memory_writemax64(cpu, data, len, odata);
236    
237     return 1;
238     }
239    
240    
241     /*
242     * devinit_8259():
243 dpavlin 12 *
244     * Initialize an 8259 PIC. Important notes:
245     *
246     * x) Most systems use _TWO_ 8259 PICs. These should be registered
247     * as separate devices.
248     *
249     * x) The irq number specified is the number used to re-calculate
250     * CPU interrupt assertions. It is _not_ the irq number at
251     * which the PIC is connected. (That is left to machine specific
252     * code in src/machine.c.)
253 dpavlin 6 */
254     int devinit_8259(struct devinit *devinit)
255     {
256     struct pic8259_data *d = malloc(sizeof(struct pic8259_data));
257     char *name2;
258 dpavlin 12 size_t nlen = strlen(devinit->name) + 20;
259 dpavlin 6
260     if (d == NULL) {
261     fprintf(stderr, "out of memory\n");
262     exit(1);
263     }
264     memset(d, 0, sizeof(struct pic8259_data));
265     d->irq_nr = devinit->irq_nr;
266    
267     name2 = malloc(nlen);
268     snprintf(name2, nlen, "%s", devinit->name);
269 dpavlin 12 if ((devinit->addr & 0xfff) == 0xa0) {
270 dpavlin 10 strlcat(name2, " [secondary]", nlen);
271 dpavlin 12 d->irq_base = 8;
272     }
273 dpavlin 6
274     memory_device_register(devinit->machine->memory, name2,
275 dpavlin 12 devinit->addr, DEV_8259_LENGTH, dev_8259_access, d,
276 dpavlin 20 DM_DEFAULT, NULL);
277 dpavlin 6
278     devinit->return_ptr = d;
279     return 1;
280     }
281    

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