src/devices/dev_8259.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_8259.c,v 1.15 2005/10/26 14:37:03 debug Exp $
 *  
 *  8259 Programmable Interrupt Controller.
 *
 *  See the following URL for more details:
 *      http://www.nondot.org/sabre/os/files/MiscHW/8259pic.txt
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "cpu.h"
#include "device.h"
#include "devices.h"
#include "emul.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


#define DEV_8259_LENGTH         2

/*  #define DEV_8259_DEBUG  */


/*
 *  dev_8259_access():
 */
int dev_8259_access(struct cpu *cpu, struct memory *mem,
        uint64_t relative_addr, unsigned char *data, size_t len,
        int writeflag, void *extra)
{
        struct pic8259_data *d = (struct pic8259_data *) extra;
        uint64_t idata = 0, odata = 0;
        int i;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

#ifdef DEV_8259_DEBUG
        if (writeflag == MEM_READ)
                fatal("[ 8259: read from 0x%x ]\n", (int)relative_addr);
        else
                fatal("[ 8259: write to 0x%x: 0x%x ]\n",
                    (int)relative_addr, (int)idata);
#endif

        switch (relative_addr) {
        case 0x00:
                if (writeflag == MEM_WRITE) {
                        if ((idata & 0x10) == 0x10) {
                                /*  Bit 3: 0=edge, 1=level  */
                                if (idata & 0x08)
                                        fatal("[ 8259: TODO: Level "
                                            "triggered (MCA bus) ]\n");
                                if (idata & 0x04)
                                        fatal("[ 8259: WARNING: Bit 2 set ]\n");
                                /*  Bit 1: 0=cascade, 1=single  */
                                /*  Bit 0: 1=4th init byte  */
                                /*  This happens on non-x86 systems:
                                    if (!(idata & 0x01))
                                        fatal("[ 8259: WARNING: Bit 0 NOT set!"
                                            "!! ]\n");  */
                                d->init_state = 1;
                                break;
                        }

                        /*  TODO: Is it ok to abort init state when there
                            is a non-init command?  */
                        if (d->init_state)
                                fatal("[ 8259: WARNING: Was in init-state, but"
                                    " it was aborted? ]\n");
                        d->init_state = 0;

                        switch (idata) {
                        case 0x0a:
                                d->current_command = 0x0a;
                                break;
                        case 0x0b:
                                d->current_command = 0x0b;
                                break;
                        case 0x0c:
                                /*  Put Master in Buffered Mode  */
                                d->current_command = 0x0c;
                                break;
                        case 0x20:      /*  End Of Interrupt  */
                                /*
                                 *  TODO: in buffered mode, is this an EOI 0?
                                 */
                                d->irr &= ~d->isr;
                                d->isr = 0;
                                /*  Recalculate interrupt assertions:  */
                                cpu_interrupt(cpu, d->irq_nr);
                                break;
                        case 0x21:      /*  Specific EOI  */
                        case 0x22:
                        case 0x23:
                        case 0x24:
                        case 0x25:
                        case 0x26:
                        case 0x27:
                        case 0x60:
                        case 0x61:
                        case 0x62:
                        case 0x63:
                        case 0x64:
                        case 0x65:
                        case 0x66:
                        case 0x67:      /*  Specific EOI  */
                                d->irr &= ~(1 << (idata & 7));
                                d->isr &= ~(1 << (idata & 7));
                                /*  Recalculate interrupt assertions:  */
                                cpu_interrupt(cpu, d->irq_nr);
                                break;
                        case 0x68:      /*  Set Special Mask Mode  */
                                /*  TODO  */
                                break;
                        case 0xc0:
                        case 0xc1:
                        case 0xc2:
                        case 0xc3:
                        case 0xc4:
                        case 0xc5:
                        case 0xc6:
                        case 0xc7:      /*  Set IRQ Priority Order  */
                                /*  TODO  */
                                break;
                        default:
                                fatal("[ 8259: unimplemented command 0x%02x"
                                    " ]\n", idata);
                                cpu->running = 0;
                        }
                } else {
                        switch (d->current_command) {
                        case 0x0a:
                                odata = d->irr;
                                break;
                        case 0x0b:
                                odata = d->isr;
                                break;
                        case 0x0c:
                                /*  Buffered mode.  */
                        default:
                                odata = 0x00;
                                for (i=0; i<8; i++)
                                        if ((d->irr >> i) & 1) {
                                                odata = 0x80 | i;
                                                break;
                                        }
                                break;
                        /*
                         *  TODO: The "default" label should really do
                         *  something like this:
                         *
                         *      fatal("[ 8259: unimplemented command 0x%02x"
                         *          " while reading ]\n", d->current_command);
                         *      cpu->running = 0;
                         *
                         *  but Linux seems to read from the secondary PIC
                         *  in a manner which works better the way things
                         *  are coded right now.
                         */
                        }
                }
                break;
        case 0x01:
                if (d->init_state > 0) {
                        if (d->init_state == 1) {
                                d->irq_base = idata & 0xf8;
                                /*  This happens on non-x86 machines:
                                    if (idata & 7)
                                        fatal("[ 8259: WARNING! Lowest"
                                            " bits in Init Cmd 1 are"
                                            " non-zero! ]\n");  */
                                d->init_state = 2;
                        } else if (d->init_state == 2) {
                                /*  Slave attachment. TODO  */
                                d->init_state = 3;
                        } else if (d->init_state == 3) {
                                if (idata & 0x02)
                                        fatal("[ 8259: WARNING! Bit 1 i"
                                            "n Init Cmd 4 is set! ]\n");
                                if (!(idata & 0x01))
                                        fatal("[ 8259: WARNING! Bit 0 "
                                            "in Init Cmd 4 is not"
                                            " set! ]\n");
                                d->init_state = 0;
                        }
                        break;
                }

                if (writeflag == MEM_WRITE) {
                        d->ier = idata;
                        /*  Recalculate interrupt assertions:  */
                        cpu_interrupt(cpu, d->irq_nr);
                } else {
                        odata = d->ier;
                }
                break;
        default:
                if (writeflag == MEM_WRITE) {
                        fatal("[ 8259: unimplemented write to address 0x%x"
                            " data=0x%02x ]\n", (int)relative_addr, (int)idata);
                        cpu->running = 0;
                } else {
                        fatal("[ 8259: unimplemented read from address 0x%x "
                            "]\n", (int)relative_addr);
                        cpu->running = 0;
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


/*
 *  devinit_8259():
 *
 *  Initialize an 8259 PIC. Important notes:
 *
 *      x)  Most systems use _TWO_ 8259 PICs. These should be registered
 *          as separate devices.
 *
 *      x)  The irq number specified is the number used to re-calculate
 *          CPU interrupt assertions.  It is _not_ the irq number at
 *          which the PIC is connected. (That is left to machine specific
 *          code in src/machine.c.)
 */
int devinit_8259(struct devinit *devinit)
{
        struct pic8259_data *d = malloc(sizeof(struct pic8259_data));
        char *name2;
        size_t nlen = strlen(devinit->name) + 20;

        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct pic8259_data));
        d->irq_nr = devinit->irq_nr;

        name2 = malloc(nlen);
        snprintf(name2, nlen, "%s", devinit->name);
        if ((devinit->addr & 0xfff) == 0xa0) {
                strlcat(name2, " [secondary]", nlen);
                d->irq_base = 8;
        }

        memory_device_register(devinit->machine->memory, name2,
            devinit->addr, DEV_8259_LENGTH, dev_8259_access, d,
            MEM_DEFAULT, NULL);

        devinit->return_ptr = d;
        return 1;
}

1	dpavlin	6	/*
2			* Copyright (C) 2005 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	18	* $Id: dev_8259.c,v 1.15 2005/10/26 14:37:03 debug Exp $
29	dpavlin	6	*
30			* 8259 Programmable Interrupt Controller.
31			*
32	dpavlin	12	* See the following URL for more details:
33	dpavlin	6	* http://www.nondot.org/sabre/os/files/MiscHW/8259pic.txt
34			*/
35
36			#include <stdio.h>
37			#include <stdlib.h>
38			#include <string.h>
39
40			#include "cpu.h"
41			#include "device.h"
42			#include "devices.h"
43			#include "emul.h"
44			#include "machine.h"
45			#include "memory.h"
46			#include "misc.h"
47
48
49			#define DEV_8259_LENGTH 2
50
51	dpavlin	12	/* #define DEV_8259_DEBUG */
52	dpavlin	6
53	dpavlin	12
54	dpavlin	6	/*
55			* dev_8259_access():
56			*/
57			int dev_8259_access(struct cpu cpu, struct memory mem,
58			uint64_t relative_addr, unsigned char *data, size_t len,
59			int writeflag, void *extra)
60			{
61			struct pic8259_data d = (struct pic8259_data ) extra;
62			uint64_t idata = 0, odata = 0;
63	dpavlin	12	int i;
64	dpavlin	6
65	dpavlin	18	if (writeflag == MEM_WRITE)
66			idata = memory_readmax64(cpu, data, len);
67	dpavlin	6
68	dpavlin	12	#ifdef DEV_8259_DEBUG
69			if (writeflag == MEM_READ)
70			fatal("[ 8259: read from 0x%x ]\n", (int)relative_addr);
71			else
72			fatal("[ 8259: write to 0x%x: 0x%x ]\n",
73			(int)relative_addr, (int)idata);
74			#endif
75
76	dpavlin	6	switch (relative_addr) {
77			case 0x00:
78			if (writeflag == MEM_WRITE) {
79			if ((idata & 0x10) == 0x10) {
80			/* Bit 3: 0=edge, 1=level */
81			if (idata & 0x08)
82			fatal("[ 8259: TODO: Level "
83			"triggered (MCA bus) ]\n");
84			if (idata & 0x04)
85			fatal("[ 8259: WARNING: Bit 2 set ]\n");
86			/* Bit 1: 0=cascade, 1=single */
87			/* Bit 0: 1=4th init byte */
88	dpavlin	12	/* This happens on non-x86 systems:
89			if (!(idata & 0x01))
90	dpavlin	6	fatal("[ 8259: WARNING: Bit 0 NOT set!"
91	dpavlin	12	"!! ]\n"); */
92	dpavlin	6	d->init_state = 1;
93			break;
94			}
95
96			/* TODO: Is it ok to abort init state when there
97			is a non-init command? */
98			if (d->init_state)
99			fatal("[ 8259: WARNING: Was in init-state, but"
100			" it was aborted? ]\n");
101			d->init_state = 0;
102
103			switch (idata) {
104			case 0x0a:
105			d->current_command = 0x0a;
106			break;
107			case 0x0b:
108			d->current_command = 0x0b;
109			break;
110	dpavlin	12	case 0x0c:
111			/* Put Master in Buffered Mode */
112			d->current_command = 0x0c;
113			break;
114	dpavlin	6	case 0x20: /* End Of Interrupt */
115	dpavlin	12	/*
116			* TODO: in buffered mode, is this an EOI 0?
117			*/
118	dpavlin	6	d->irr &= ~d->isr;
119			d->isr = 0;
120			/* Recalculate interrupt assertions: */
121	dpavlin	12	cpu_interrupt(cpu, d->irq_nr);
122	dpavlin	6	break;
123	dpavlin	12	case 0x21: /* Specific EOI */
124			case 0x22:
125			case 0x23:
126			case 0x24:
127			case 0x25:
128			case 0x26:
129			case 0x27:
130	dpavlin	6	case 0x60:
131			case 0x61:
132			case 0x62:
133			case 0x63:
134			case 0x64:
135			case 0x65:
136			case 0x66:
137			case 0x67: /* Specific EOI */
138			d->irr &= ~(1 << (idata & 7));
139			d->isr &= ~(1 << (idata & 7));
140			/* Recalculate interrupt assertions: */
141	dpavlin	12	cpu_interrupt(cpu, d->irq_nr);
142	dpavlin	6	break;
143			case 0x68: /* Set Special Mask Mode */
144			/* TODO */
145			break;
146			case 0xc0:
147			case 0xc1:
148			case 0xc2:
149			case 0xc3:
150			case 0xc4:
151			case 0xc5:
152			case 0xc6:
153			case 0xc7: /* Set IRQ Priority Order */
154			/* TODO */
155			break;
156			default:
157			fatal("[ 8259: unimplemented command 0x%02x"
158			" ]\n", idata);
159			cpu->running = 0;
160			}
161			} else {
162			switch (d->current_command) {
163			case 0x0a:
164			odata = d->irr;
165			break;
166			case 0x0b:
167			odata = d->isr;
168			break;
169	dpavlin	12	case 0x0c:
170			/* Buffered mode. */
171	dpavlin	6	default:
172	dpavlin	12	odata = 0x00;
173			for (i=0; i<8; i++)
174			if ((d->irr >> i) & 1) {
175			odata = 0x80 \| i;
176			break;
177			}
178			break;
179			/*
180			* TODO: The "default" label should really do
181			* something like this:
182			*
183			* fatal("[ 8259: unimplemented command 0x%02x"
184			* " while reading ]\n", d->current_command);
185			* cpu->running = 0;
186			*
187			* but Linux seems to read from the secondary PIC
188			* in a manner which works better the way things
189			* are coded right now.
190			*/
191	dpavlin	6	}
192			}
193			break;
194			case 0x01:
195			if (d->init_state > 0) {
196			if (d->init_state == 1) {
197			d->irq_base = idata & 0xf8;
198	dpavlin	12	/* This happens on non-x86 machines:
199			if (idata & 7)
200	dpavlin	6	fatal("[ 8259: WARNING! Lowest"
201			" bits in Init Cmd 1 are"
202	dpavlin	12	" non-zero! ]\n"); */
203	dpavlin	6	d->init_state = 2;
204			} else if (d->init_state == 2) {
205			/* Slave attachment. TODO */
206			d->init_state = 3;
207			} else if (d->init_state == 3) {
208			if (idata & 0x02)
209			fatal("[ 8259: WARNING! Bit 1 i"
210			"n Init Cmd 4 is set! ]\n");
211			if (!(idata & 0x01))
212			fatal("[ 8259: WARNING! Bit 0 "
213			"in Init Cmd 4 is not"
214			" set! ]\n");
215			d->init_state = 0;
216			}
217			break;
218			}
219
220			if (writeflag == MEM_WRITE) {
221			d->ier = idata;
222			/* Recalculate interrupt assertions: */
223	dpavlin	12	cpu_interrupt(cpu, d->irq_nr);
224	dpavlin	6	} else {
225			odata = d->ier;
226			}
227			break;
228			default:
229			if (writeflag == MEM_WRITE) {
230			fatal("[ 8259: unimplemented write to address 0x%x"
231			" data=0x%02x ]\n", (int)relative_addr, (int)idata);
232			cpu->running = 0;
233			} else {
234			fatal("[ 8259: unimplemented read from address 0x%x "
235			"]\n", (int)relative_addr);
236			cpu->running = 0;
237			}
238			}
239
240			if (writeflag == MEM_READ)
241			memory_writemax64(cpu, data, len, odata);
242
243			return 1;
244			}
245
246
247			/*
248			* devinit_8259():
249	dpavlin	12	*
250			* Initialize an 8259 PIC. Important notes:
251			*
252			* x) Most systems use _TWO_ 8259 PICs. These should be registered
253			* as separate devices.
254			*
255			* x) The irq number specified is the number used to re-calculate
256			* CPU interrupt assertions. It is _not_ the irq number at
257			* which the PIC is connected. (That is left to machine specific
258			* code in src/machine.c.)
259	dpavlin	6	*/
260			int devinit_8259(struct devinit *devinit)
261			{
262			struct pic8259_data *d = malloc(sizeof(struct pic8259_data));
263			char *name2;
264	dpavlin	12	size_t nlen = strlen(devinit->name) + 20;
265	dpavlin	6
266			if (d == NULL) {
267			fprintf(stderr, "out of memory\n");
268			exit(1);
269			}
270			memset(d, 0, sizeof(struct pic8259_data));
271			d->irq_nr = devinit->irq_nr;
272
273			name2 = malloc(nlen);
274			snprintf(name2, nlen, "%s", devinit->name);
275	dpavlin	12	if ((devinit->addr & 0xfff) == 0xa0) {
276	dpavlin	10	strlcat(name2, " [secondary]", nlen);
277	dpavlin	12	d->irq_base = 8;
278			}
279	dpavlin	6
280			memory_device_register(devinit->machine->memory, name2,
281	dpavlin	12	devinit->addr, DEV_8259_LENGTH, dev_8259_access, d,
282	dpavlin	6	MEM_DEFAULT, NULL);
283
284			devinit->return_ptr = d;
285			return 1;
286			}
287