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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_8253.c,v 1.13 2006/07/21 16:55:41 debug Exp $ |
* $Id: dev_8253.c,v 1.18 2006/12/30 13:30:57 debug Exp $ |
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* |
* |
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* Intel 8253/8254 Programmable Interval Timer |
* Intel 8253/8254 Programmable Interval Timer |
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* |
* |
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* TODO: The timers don't really count down. Fix this when there is a generic |
* TODO/NOTE: |
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* clock framework; also split counter[] into reset value and current value. |
* The timers don't really count down. Timer 0 causes clock interrupts |
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* at a specific frequency, but reading the counter register would not |
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* result in anything meaningful. |
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* |
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* (Split counter[] into reset value and current value.) |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#include "cpu.h" |
#include "cpu.h" |
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#include "device.h" |
#include "device.h" |
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#include "devices.h" |
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#include "emul.h" |
#include "emul.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "timer.h" |
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#include "i8253reg.h" |
#include "i8253reg.h" |
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/* #define debug fatal */ |
#define debug fatal |
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#define DEV_8253_LENGTH 4 |
#define DEV_8253_LENGTH 4 |
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#define TICK_SHIFT 14 |
#define TICK_SHIFT 14 |
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struct pit8253_data { |
struct pit8253_data { |
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int in_use; |
int in_use; |
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int irq0_nr; |
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int counter_select; |
int counter_select; |
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uint8_t mode_byte; |
uint8_t mode_byte; |
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int mode[3]; |
int mode[3]; |
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int counter[3]; |
int counter[3]; |
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int hz[3]; |
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struct timer *timer0; |
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struct interrupt irq; |
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int pending_interrupts_timer0; |
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}; |
}; |
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static void timer0_tick(struct timer *t, void *extra) |
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{ |
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struct pit8253_data *d = (struct pit8253_data *) extra; |
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d->pending_interrupts_timer0 ++; |
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#if 0 |
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printf("%i ", d->pending_interrupts_timer0); fflush(stdout); |
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#endif |
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} |
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DEVICE_TICK(8253) |
DEVICE_TICK(8253) |
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{ |
{ |
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struct pit8253_data *d = (struct pit8253_data *) extra; |
struct pit8253_data *d = (struct pit8253_data *) extra; |
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return; |
return; |
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switch (d->mode[0] & 0x0e) { |
switch (d->mode[0] & 0x0e) { |
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case I8253_TIMER_INTTC: |
case I8253_TIMER_INTTC: |
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/* TODO: Correct frequency! */ |
if (d->pending_interrupts_timer0 > 0) |
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cpu_interrupt(cpu, d->irq0_nr); |
INTERRUPT_ASSERT(d->irq); |
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break; |
break; |
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case I8253_TIMER_SQWAVE: |
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case I8253_TIMER_RATEGEN: |
case I8253_TIMER_RATEGEN: |
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break; |
break; |
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default:fatal("[ 8253: unimplemented mode 0x%x ]\n", d->mode[0] & 0x0e); |
default:fatal("[ 8253: unimplemented mode 0x%x ]\n", d->mode[0] & 0x0e); |
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exit(1); |
exit(1); |
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} |
} |
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d->in_use = 1; |
d->in_use = 1; |
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/* TODO: ack somewhere else */ |
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cpu_interrupt_ack(cpu, d->irq0_nr); |
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switch (relative_addr) { |
switch (relative_addr) { |
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case I8253_TIMER_CNTR0: |
case I8253_TIMER_CNTR0: |
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case I8253_TIMER_MSB: |
case I8253_TIMER_MSB: |
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d->counter[relative_addr] &= 0x00ff; |
d->counter[relative_addr] &= 0x00ff; |
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d->counter[relative_addr] |= ((idata&0xff)<<8); |
d->counter[relative_addr] |= ((idata&0xff)<<8); |
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if (d->counter[relative_addr] != 0) |
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d->hz[relative_addr] = |
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I8253_TIMER_FREQ / (float) |
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d->counter[relative_addr] + 0.5; |
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else |
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d->hz[relative_addr] = 0; |
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debug("[ 8253: counter %i set to %i (%i Hz) " |
debug("[ 8253: counter %i set to %i (%i Hz) " |
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"]\n", relative_addr, d->counter[ |
"]\n", relative_addr, d->counter[ |
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relative_addr], (int)(I8253_TIMER_FREQ / |
relative_addr], d->hz[relative_addr]); |
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(float)d->counter[relative_addr] + 0.5)); |
switch (relative_addr) { |
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case 0: if (d->timer0 == NULL) |
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d->timer0 = timer_add( |
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d->hz[0], timer0_tick, d); |
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else |
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timer_update_frequency( |
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d->timer0, d->hz[0]); |
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break; |
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case 1: fatal("TODO: DMA refresh?\n"); |
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exit(1); |
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case 2: fatal("TODO: 8253 tone generation?\n"); |
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break; |
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} |
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break; |
break; |
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default:fatal("[ 8253: huh? writing to counter" |
default:fatal("[ 8253: huh? writing to counter" |
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" %i but neither from msb nor lsb? ]\n", |
" %i but neither from msb nor lsb? ]\n", |
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exit(1); |
exit(1); |
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} |
} |
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memset(d, 0, sizeof(struct pit8253_data)); |
memset(d, 0, sizeof(struct pit8253_data)); |
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d->irq0_nr = devinit->irq_nr; |
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d->in_use = devinit->in_use; |
d->in_use = devinit->in_use; |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
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/* Don't cause interrupt, by default. */ |
/* Don't cause interrupt, by default. */ |
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d->mode[0] = I8253_TIMER_RATEGEN; |
d->mode[0] = I8253_TIMER_RATEGEN; |
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d->mode[1] = I8253_TIMER_RATEGEN; |
d->mode[1] = I8253_TIMER_RATEGEN; |
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d->mode[2] = I8253_TIMER_RATEGEN; |
d->mode[2] = I8253_TIMER_RATEGEN; |
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devinit->machine->isa_pic_data.pending_timer_interrupts = |
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&d->pending_interrupts_timer0; |
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memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d, |
devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d, |
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DM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |