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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_8253.c,v 1.16 2006/08/22 15:13:03 debug Exp $ |
* $Id: dev_8253.c,v 1.18 2006/12/30 13:30:57 debug Exp $ |
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* |
* |
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* Intel 8253/8254 Programmable Interval Timer |
* Intel 8253/8254 Programmable Interval Timer |
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* |
* |
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#include "cpu.h" |
#include "cpu.h" |
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#include "device.h" |
#include "device.h" |
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#include "emul.h" |
#include "emul.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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int hz[3]; |
int hz[3]; |
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struct timer *timer0; |
struct timer *timer0; |
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int irq0_nr; |
struct interrupt irq; |
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int pending_interrupts_timer0; |
int pending_interrupts_timer0; |
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}; |
}; |
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case I8253_TIMER_INTTC: |
case I8253_TIMER_INTTC: |
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if (d->pending_interrupts_timer0 > 0) |
if (d->pending_interrupts_timer0 > 0) |
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cpu_interrupt(cpu, d->irq0_nr); |
INTERRUPT_ASSERT(d->irq); |
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break; |
break; |
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case I8253_TIMER_SQWAVE: |
case I8253_TIMER_SQWAVE: |
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exit(1); |
exit(1); |
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} |
} |
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memset(d, 0, sizeof(struct pit8253_data)); |
memset(d, 0, sizeof(struct pit8253_data)); |
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d->irq0_nr = devinit->irq_nr; |
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d->in_use = devinit->in_use; |
d->in_use = devinit->in_use; |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
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/* Don't cause interrupt, by default. */ |
/* Don't cause interrupt, by default. */ |
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d->mode[0] = I8253_TIMER_RATEGEN; |
d->mode[0] = I8253_TIMER_RATEGEN; |
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d->mode[1] = I8253_TIMER_RATEGEN; |
d->mode[1] = I8253_TIMER_RATEGEN; |