/[gxemul]/trunk/src/devices/dev_8253.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Annotation of /trunk/src/devices/dev_8253.c

Parent Directory Parent Directory | Revision Log Revision Log

Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 7049 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 dpavlin 6 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 6 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: dev_8253.c,v 1.18 2006/12/30 13:30:57 debug Exp $
29 dpavlin 6 *
30 dpavlin 28 * Intel 8253/8254 Programmable Interval Timer
31     *
32 dpavlin 32 * TODO/NOTE:
33     * The timers don't really count down. Timer 0 causes clock interrupts
34     * at a specific frequency, but reading the counter register would not
35     * result in anything meaningful.
36     *
37     * (Split counter[] into reset value and current value.)
38 dpavlin 6 */
39    
40     #include <stdio.h>
41     #include <stdlib.h>
42     #include <string.h>
43    
44     #include "cpu.h"
45     #include "device.h"
46     #include "emul.h"
47 dpavlin 34 #include "interrupt.h"
48 dpavlin 6 #include "machine.h"
49     #include "memory.h"
50     #include "misc.h"
51 dpavlin 32 #include "timer.h"
52 dpavlin 6
53 dpavlin 28 #include "i8253reg.h"
54 dpavlin 6
55 dpavlin 28
56 dpavlin 32 #define debug fatal
57 dpavlin 28
58 dpavlin 6 #define DEV_8253_LENGTH 4
59     #define TICK_SHIFT 14
60    
61    
62     struct pit8253_data {
63 dpavlin 20 int in_use;
64 dpavlin 28
65 dpavlin 6 int counter_select;
66 dpavlin 28 uint8_t mode_byte;
67    
68     int mode[3];
69     int counter[3];
70 dpavlin 32
71     int hz[3];
72    
73     struct timer *timer0;
74 dpavlin 34 struct interrupt irq;
75 dpavlin 32 int pending_interrupts_timer0;
76 dpavlin 6 };
77    
78    
79 dpavlin 32 static void timer0_tick(struct timer *t, void *extra)
80     {
81     struct pit8253_data *d = (struct pit8253_data *) extra;
82     d->pending_interrupts_timer0 ++;
83    
84     #if 0
85     printf("%i ", d->pending_interrupts_timer0); fflush(stdout);
86     #endif
87     }
88    
89    
90 dpavlin 28 DEVICE_TICK(8253)
91 dpavlin 6 {
92     struct pit8253_data *d = (struct pit8253_data *) extra;
93 dpavlin 20
94     if (!d->in_use)
95     return;
96    
97 dpavlin 28 switch (d->mode[0] & 0x0e) {
98 dpavlin 30
99 dpavlin 28 case I8253_TIMER_INTTC:
100 dpavlin 32 if (d->pending_interrupts_timer0 > 0)
101 dpavlin 34 INTERRUPT_ASSERT(d->irq);
102 dpavlin 28 break;
103 dpavlin 30
104 dpavlin 32 case I8253_TIMER_SQWAVE:
105 dpavlin 28 case I8253_TIMER_RATEGEN:
106     break;
107 dpavlin 30
108 dpavlin 28 default:fatal("[ 8253: unimplemented mode 0x%x ]\n", d->mode[0] & 0x0e);
109     exit(1);
110     }
111 dpavlin 6 }
112    
113    
114 dpavlin 22 DEVICE_ACCESS(8253)
115 dpavlin 6 {
116     struct pit8253_data *d = (struct pit8253_data *) extra;
117     uint64_t idata = 0, odata = 0;
118    
119 dpavlin 18 if (writeflag == MEM_WRITE)
120     idata = memory_readmax64(cpu, data, len);
121 dpavlin 6
122 dpavlin 20 d->in_use = 1;
123    
124 dpavlin 6 switch (relative_addr) {
125 dpavlin 28
126     case I8253_TIMER_CNTR0:
127     case I8253_TIMER_CNTR1:
128     case I8253_TIMER_CNTR2:
129 dpavlin 6 if (writeflag == MEM_WRITE) {
130 dpavlin 28 switch (d->mode_byte & 0x30) {
131     case I8253_TIMER_LSB:
132     case I8253_TIMER_16BIT:
133     d->counter[relative_addr] &= 0xff00;
134     d->counter[relative_addr] |= (idata & 0xff);
135     break;
136     case I8253_TIMER_MSB:
137     d->counter[relative_addr] &= 0x00ff;
138     d->counter[relative_addr] |= ((idata&0xff)<<8);
139 dpavlin 32 if (d->counter[relative_addr] != 0)
140     d->hz[relative_addr] =
141     I8253_TIMER_FREQ / (float)
142     d->counter[relative_addr] + 0.5;
143     else
144     d->hz[relative_addr] = 0;
145 dpavlin 28 debug("[ 8253: counter %i set to %i (%i Hz) "
146     "]\n", relative_addr, d->counter[
147 dpavlin 32 relative_addr], d->hz[relative_addr]);
148     switch (relative_addr) {
149     case 0: if (d->timer0 == NULL)
150     d->timer0 = timer_add(
151     d->hz[0], timer0_tick, d);
152     else
153     timer_update_frequency(
154     d->timer0, d->hz[0]);
155     break;
156     case 1: fatal("TODO: DMA refresh?\n");
157     exit(1);
158     case 2: fatal("TODO: 8253 tone generation?\n");
159     break;
160     }
161 dpavlin 28 break;
162     default:fatal("[ 8253: huh? writing to counter"
163     " %i but neither from msb nor lsb? ]\n",
164     relative_addr);
165     }
166 dpavlin 6 } else {
167 dpavlin 28 switch (d->mode_byte & 0x30) {
168     case I8253_TIMER_LSB:
169     case I8253_TIMER_16BIT:
170     odata = d->counter[relative_addr] & 0xff;
171     break;
172     case I8253_TIMER_MSB:
173     odata = (d->counter[relative_addr] >> 8) & 0xff;
174     break;
175     default:fatal("[ 8253: huh? reading from counter"
176     " %i but neither from msb nor lsb? ]\n",
177     relative_addr);
178     }
179 dpavlin 6 }
180 dpavlin 28
181     /* Switch from LSB to MSB, if accessing as 16-bit word: */
182     if ((d->mode_byte & 0x30) == I8253_TIMER_16BIT)
183     d->mode_byte &= ~I8253_TIMER_LSB;
184    
185 dpavlin 6 break;
186 dpavlin 28
187     case I8253_TIMER_MODE:
188 dpavlin 6 if (writeflag == MEM_WRITE) {
189 dpavlin 28 d->mode_byte = idata;
190    
191 dpavlin 6 d->counter_select = idata >> 6;
192 dpavlin 28 if (d->counter_select > 2) {
193     debug("[ 8253: attempt to select counter 3,"
194     " which doesn't exist. ]\n");
195     d->counter_select = 0;
196     }
197    
198     d->mode[d->counter_select] = idata & 0x0e;
199    
200     debug("[ 8253: select=%i mode=0x%x ",
201     d->counter_select, d->mode[d->counter_select]);
202     if (idata & 0x30) {
203     switch (idata & 0x30) {
204     case I8253_TIMER_LSB:
205     debug("LSB ");
206     break;
207     case I8253_TIMER_16BIT:
208     debug("LSB+");
209     case I8253_TIMER_MSB:
210     debug("MSB ");
211     }
212     }
213     debug("]\n");
214    
215     if (idata & I8253_TIMER_BCD) {
216     fatal("[ 8253: BCD not yet implemented ]\n");
217     exit(1);
218     }
219 dpavlin 6 } else {
220 dpavlin 28 debug("[ 8253: read; can this actually happen? ]\n");
221     odata = d->mode_byte;
222 dpavlin 6 }
223     break;
224 dpavlin 28
225     default:if (writeflag == MEM_WRITE) {
226 dpavlin 6 fatal("[ 8253: unimplemented write to address 0x%x"
227     " data=0x%02x ]\n", (int)relative_addr, (int)idata);
228     } else {
229     fatal("[ 8253: unimplemented read from address 0x%x "
230     "]\n", (int)relative_addr);
231     }
232 dpavlin 28 exit(1);
233 dpavlin 6 }
234    
235     if (writeflag == MEM_READ)
236     memory_writemax64(cpu, data, len, odata);
237    
238     return 1;
239     }
240    
241    
242 dpavlin 22 DEVINIT(8253)
243 dpavlin 6 {
244     struct pit8253_data *d = malloc(sizeof(struct pit8253_data));
245    
246     if (d == NULL) {
247     fprintf(stderr, "out of memory\n");
248     exit(1);
249     }
250     memset(d, 0, sizeof(struct pit8253_data));
251 dpavlin 34
252 dpavlin 20 d->in_use = devinit->in_use;
253 dpavlin 6
254 dpavlin 34 INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
255    
256 dpavlin 28 /* Don't cause interrupt, by default. */
257     d->mode[0] = I8253_TIMER_RATEGEN;
258     d->mode[1] = I8253_TIMER_RATEGEN;
259     d->mode[2] = I8253_TIMER_RATEGEN;
260    
261 dpavlin 32 devinit->machine->isa_pic_data.pending_timer_interrupts =
262     &d->pending_interrupts_timer0;
263    
264 dpavlin 6 memory_device_register(devinit->machine->memory, devinit->name,
265     devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d,
266 dpavlin 20 DM_DEFAULT, NULL);
267 dpavlin 6
268     machine_add_tickfunction(devinit->machine, dev_8253_tick,
269 dpavlin 24 d, TICK_SHIFT, 0.0);
270 dpavlin 6
271     return 1;
272     }
273    
  ViewVC Help
Powered by ViewVC 1.1.26