/[gxemul]/trunk/src/devices/dev_8253.c
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Annotation of /trunk/src/devices/dev_8253.c

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 6083 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============
1 dpavlin 6 /*
2 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 dpavlin 6 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 28 * $Id: dev_8253.c,v 1.13 2006/07/21 16:55:41 debug Exp $
29 dpavlin 6 *
30 dpavlin 28 * Intel 8253/8254 Programmable Interval Timer
31     *
32     * TODO: The timers don't really count down. Fix this when there is a generic
33     * clock framework; also split counter[] into reset value and current value.
34 dpavlin 6 */
35    
36     #include <stdio.h>
37     #include <stdlib.h>
38     #include <string.h>
39    
40     #include "cpu.h"
41     #include "device.h"
42     #include "devices.h"
43     #include "emul.h"
44     #include "machine.h"
45     #include "memory.h"
46     #include "misc.h"
47    
48 dpavlin 28 #include "i8253reg.h"
49 dpavlin 6
50 dpavlin 28
51     /* #define debug fatal */
52    
53 dpavlin 6 #define DEV_8253_LENGTH 4
54     #define TICK_SHIFT 14
55    
56    
57     struct pit8253_data {
58 dpavlin 20 int in_use;
59 dpavlin 28
60     int irq0_nr;
61 dpavlin 6 int counter_select;
62 dpavlin 28 uint8_t mode_byte;
63    
64     int mode[3];
65     int counter[3];
66 dpavlin 6 };
67    
68    
69 dpavlin 28 DEVICE_TICK(8253)
70 dpavlin 6 {
71     struct pit8253_data *d = (struct pit8253_data *) extra;
72 dpavlin 20
73     if (!d->in_use)
74     return;
75    
76 dpavlin 28 switch (d->mode[0] & 0x0e) {
77     case I8253_TIMER_INTTC:
78     /* TODO: Correct frequency! */
79     cpu_interrupt(cpu, d->irq0_nr);
80     break;
81     case I8253_TIMER_RATEGEN:
82     break;
83     default:fatal("[ 8253: unimplemented mode 0x%x ]\n", d->mode[0] & 0x0e);
84     exit(1);
85     }
86 dpavlin 6 }
87    
88    
89 dpavlin 22 DEVICE_ACCESS(8253)
90 dpavlin 6 {
91     struct pit8253_data *d = (struct pit8253_data *) extra;
92     uint64_t idata = 0, odata = 0;
93    
94 dpavlin 18 if (writeflag == MEM_WRITE)
95     idata = memory_readmax64(cpu, data, len);
96 dpavlin 6
97 dpavlin 20 d->in_use = 1;
98    
99 dpavlin 6 /* TODO: ack somewhere else */
100 dpavlin 28 cpu_interrupt_ack(cpu, d->irq0_nr);
101 dpavlin 6
102     switch (relative_addr) {
103 dpavlin 28
104     case I8253_TIMER_CNTR0:
105     case I8253_TIMER_CNTR1:
106     case I8253_TIMER_CNTR2:
107 dpavlin 6 if (writeflag == MEM_WRITE) {
108 dpavlin 28 switch (d->mode_byte & 0x30) {
109     case I8253_TIMER_LSB:
110     case I8253_TIMER_16BIT:
111     d->counter[relative_addr] &= 0xff00;
112     d->counter[relative_addr] |= (idata & 0xff);
113     break;
114     case I8253_TIMER_MSB:
115     d->counter[relative_addr] &= 0x00ff;
116     d->counter[relative_addr] |= ((idata&0xff)<<8);
117     debug("[ 8253: counter %i set to %i (%i Hz) "
118     "]\n", relative_addr, d->counter[
119     relative_addr], (int)(I8253_TIMER_FREQ /
120     (float)d->counter[relative_addr] + 0.5));
121     break;
122     default:fatal("[ 8253: huh? writing to counter"
123     " %i but neither from msb nor lsb? ]\n",
124     relative_addr);
125     }
126 dpavlin 6 } else {
127 dpavlin 28 switch (d->mode_byte & 0x30) {
128     case I8253_TIMER_LSB:
129     case I8253_TIMER_16BIT:
130     odata = d->counter[relative_addr] & 0xff;
131     break;
132     case I8253_TIMER_MSB:
133     odata = (d->counter[relative_addr] >> 8) & 0xff;
134     break;
135     default:fatal("[ 8253: huh? reading from counter"
136     " %i but neither from msb nor lsb? ]\n",
137     relative_addr);
138     }
139 dpavlin 6 }
140 dpavlin 28
141     /* Switch from LSB to MSB, if accessing as 16-bit word: */
142     if ((d->mode_byte & 0x30) == I8253_TIMER_16BIT)
143     d->mode_byte &= ~I8253_TIMER_LSB;
144    
145 dpavlin 6 break;
146 dpavlin 28
147     case I8253_TIMER_MODE:
148 dpavlin 6 if (writeflag == MEM_WRITE) {
149 dpavlin 28 d->mode_byte = idata;
150    
151 dpavlin 6 d->counter_select = idata >> 6;
152 dpavlin 28 if (d->counter_select > 2) {
153     debug("[ 8253: attempt to select counter 3,"
154     " which doesn't exist. ]\n");
155     d->counter_select = 0;
156     }
157    
158     d->mode[d->counter_select] = idata & 0x0e;
159    
160     debug("[ 8253: select=%i mode=0x%x ",
161     d->counter_select, d->mode[d->counter_select]);
162     if (idata & 0x30) {
163     switch (idata & 0x30) {
164     case I8253_TIMER_LSB:
165     debug("LSB ");
166     break;
167     case I8253_TIMER_16BIT:
168     debug("LSB+");
169     case I8253_TIMER_MSB:
170     debug("MSB ");
171     }
172     }
173     debug("]\n");
174    
175     if (idata & I8253_TIMER_BCD) {
176     fatal("[ 8253: BCD not yet implemented ]\n");
177     exit(1);
178     }
179 dpavlin 6 } else {
180 dpavlin 28 debug("[ 8253: read; can this actually happen? ]\n");
181     odata = d->mode_byte;
182 dpavlin 6 }
183     break;
184 dpavlin 28
185     default:if (writeflag == MEM_WRITE) {
186 dpavlin 6 fatal("[ 8253: unimplemented write to address 0x%x"
187     " data=0x%02x ]\n", (int)relative_addr, (int)idata);
188     } else {
189     fatal("[ 8253: unimplemented read from address 0x%x "
190     "]\n", (int)relative_addr);
191     }
192 dpavlin 28 exit(1);
193 dpavlin 6 }
194    
195     if (writeflag == MEM_READ)
196     memory_writemax64(cpu, data, len, odata);
197    
198     return 1;
199     }
200    
201    
202 dpavlin 22 DEVINIT(8253)
203 dpavlin 6 {
204     struct pit8253_data *d = malloc(sizeof(struct pit8253_data));
205    
206     if (d == NULL) {
207     fprintf(stderr, "out of memory\n");
208     exit(1);
209     }
210     memset(d, 0, sizeof(struct pit8253_data));
211 dpavlin 28 d->irq0_nr = devinit->irq_nr;
212 dpavlin 20 d->in_use = devinit->in_use;
213 dpavlin 6
214 dpavlin 28 /* Don't cause interrupt, by default. */
215     d->mode[0] = I8253_TIMER_RATEGEN;
216     d->mode[1] = I8253_TIMER_RATEGEN;
217     d->mode[2] = I8253_TIMER_RATEGEN;
218    
219 dpavlin 6 memory_device_register(devinit->machine->memory, devinit->name,
220     devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d,
221 dpavlin 20 DM_DEFAULT, NULL);
222 dpavlin 6
223     machine_add_tickfunction(devinit->machine, dev_8253_tick,
224 dpavlin 24 d, TICK_SHIFT, 0.0);
225 dpavlin 6
226     return 1;
227     }
228    
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