/[gxemul]/trunk/src/devices/bus_pci.c
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Diff of /trunk/src/devices/bus_pci.c

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revision 42 by dpavlin, Mon Oct 8 16:22:32 2007 UTC revision 62 by dpavlin, Sat Oct 13 12:51:47 2007 UTC
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: bus_pci.c,v 1.84 2007/06/15 18:13:04 debug Exp $   *  $Id: bus_pci.c,v 1.85 2007/06/16 14:39:18 debug Exp $
29   *     *  
30   *  COMMENT: Generic PCI bus framework   *  COMMENT: Generic PCI bus framework
31   *   *
# Line 207  void bus_pci_setaddr(struct cpu *cpu, st Line 207  void bus_pci_setaddr(struct cpu *cpu, st
207          pci_data->cur_device = device;          pci_data->cur_device = device;
208          pci_data->cur_func = function;          pci_data->cur_func = function;
209          pci_data->cur_reg = reg;          pci_data->cur_reg = reg;
210            debug("bus_pci_setaddr( bus %d device 0x%x func 0x%x reg 0x%x )\n", bus, device, function, reg );
211  }  }
212    
213    
# Line 384  struct pci_data *bus_pci_init(struct mac Line 385  struct pci_data *bus_pci_init(struct mac
385                  d->cur_pci_membase  += 0x10000;                  d->cur_pci_membase  += 0x10000;
386          }          }
387    
388            debug("bus_pci_init( pci_actual_io_offset %x pci_actual_mem_offset 0x%x pci_portbase 0x%x pci_membase 0x%x isa_portbase %x isa_membase %x )\n", pci_actual_io_offset, pci_actual_mem_offset, pci_portbase, pci_membase, isa_portbase, isa_membase );
389    
390          return d;          return d;
391  }  }
392    
# Line 912  PCIINIT(heuricon_pmppc) Line 915  PCIINIT(heuricon_pmppc)
915              PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));              PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
916  }  }
917    
918    /*
919     * Sandpoint host bridge based on uninorth
920     */
921    
922    #define PCI_VENDOR_MOT                  0x1057
923    #define PCI_DEVICE_ID_MOTOROLA_MPC106   0x0002
924    #define PCI_DEVICE_ID_MOTOROLA_MPC107   0x0004
925    
926    PCIINIT(mpc10x)
927    {
928            uint64_t port, memaddr;
929    
930            debug("sandpoint mpx10x host bridge\n");
931    
932            PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_MOT,
933                PCI_DEVICE_ID_MOTOROLA_MPC107));    /* FIXME MPC106 ?? */
934    
935            PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
936                PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x00);   /*  Revision?  */
937    
938            PCI_SET_DATA(PCI_BHLC_REG,
939                PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
940    
941            allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
942            allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
943            allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
944            allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
945    
946    }
947    
948    
949    
950  /*  /*
# Line 1094  PCIINIT(symphony_82c105) Line 1127  PCIINIT(symphony_82c105)
1127          /*  channel 0 and 1 enabled  */          /*  channel 0 and 1 enabled  */
1128          PCI_SET_DATA(0x40, 0x00000003);          PCI_SET_DATA(0x40, 0x00000003);
1129    
1130          CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct symphony_82c105_extra)));          CHECK_ALLOCATION(pd->extra =
1131                malloc(sizeof(struct symphony_82c105_extra)));
1132          ((struct symphony_82c105_extra *)pd->extra)->wdc0 = NULL;          ((struct symphony_82c105_extra *)pd->extra)->wdc0 = NULL;
1133          ((struct symphony_82c105_extra *)pd->extra)->wdc1 = NULL;          ((struct symphony_82c105_extra *)pd->extra)->wdc1 = NULL;
1134    
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