src/cpus/memory_x86.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: memory_x86.c,v 1.3 2006/06/24 21:47:23 debug Exp $
 *
 *  Included from cpu_x86.c.
 *
 *
 *  TODO: This is basically just a skeleton so far.
 */


/*
 *  translate_v2p():
 *
 *  Return values:
 *      0  Failure
 *      1  Success, the page is readable only
 *      2  Success, the page is read/write
 */
int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags)
{
        unsigned char pded[4];
        unsigned char pted[4];
        uint64_t table_addr;
        uint32_t pte=0, pde=0;
        int a, b, res, writable, usermode = 0;
        int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ;
        int no_exceptions = flags & FLAG_NOEXCEPTIONS;
        int no_segmentation = flags & NO_SEGMENTATION;
        struct descriptor_cache *dc;

        if (cpu->cd.x86.cursegment < 0 || cpu->cd.x86.cursegment >= 8) {
                fatal("TODO: Weird x86 segment nr %i\n",
                    cpu->cd.x86.cursegment);
                cpu->running = 0;
                return 0;
        }

        if ((vaddr >> 32) == 0xffffffff)
                vaddr &= 0xffffffff;

        dc = &cpu->cd.x86.descr_cache[cpu->cd.x86.cursegment & 7];

        if (no_segmentation) {
                /*  linear address  */
                writable = 1;
        } else {
                if (PROTECTED_MODE && vaddr > dc->limit) {
                        fatal("TODO: vaddr=0x%"PRIx64" > limit (0x%"PRIx64")\n",
                            (uint64_t) vaddr, (uint64_t) dc->limit);
                        /*  goto fail;  */
                }

                /*  TODO: Check the Privilege Level  */
                vaddr = (vaddr + dc->base) & 0xffffffff;
                writable = dc->writable;
        }

        usermode = (cpu->cd.x86.s[X86_S_CS] & X86_PL_MASK) ==
            X86_RING3;

        /*  Paging:  */
        if (cpu->cd.x86.cr[0] & X86_CR0_PG) {
                /*  TODO: This should be cached somewhere, in some
                        kind of simulated TLB.  */
                if (cpu->cd.x86.cr[3] & 0xfff) {
                        fatal("TODO: cr3=%016"PRIx64" (lowest bits non-zero)\n",
                            (uint64_t) cpu->cd.x86.cr[3]);
                        goto fail;
                }

                a = (vaddr >> 22) & 1023;
                b = (vaddr >> 12) & 1023;
                /*  fatal("vaddr = 0x%08x ==> %i, %i\n", (int)vaddr, a, b);  */

                /*  Read the Page Directory Entry:  */
                table_addr = cpu->cd.x86.cr[3] & ~0xfff;
                if (table_addr == 0)
                        fatal("WARNING: The page directory (cr3) is at"
                            " physical address 0 (?)\n");
                res = cpu->memory_rw(cpu, cpu->mem, table_addr + 4*a, pded,
                    sizeof(pded), MEM_READ, PHYSICAL);
                if (!res) {
                        fatal("TODO: could not read pde (table = 0x%"PRIx64
                            ")\n", (uint64_t) table_addr);
                        goto fail;
                }
                if ((pded[0] & 0x01) && !(pded[0] & 0x20)) {
                        pded[0] |= 0x20;
                        cpu->memory_rw(cpu, cpu->mem, table_addr + 4*a, pded,
                            sizeof(pded), MEM_WRITE, PHYSICAL);
                }
                if ((pded[0] & 0x01) && writeflag == MEM_WRITE &&
                    !(pded[0] & 0x40)) {
                        pded[0] |= 0x40;
                        cpu->memory_rw(cpu, cpu->mem, table_addr + 4*a, pded,
                            sizeof(pded), MEM_WRITE, PHYSICAL);
                }
                pde = pded[0] + (pded[1] << 8) + (pded[2] << 16) +
                    (pded[3] << 24);
                /*  fatal("  pde: 0x%08x\n", (int)pde);  */
                /*  TODO: lowest bits of the pde  */
                if (!(pde & 0x01)) {
                        fatal("PAGE FAULT: pde not present: vaddr=0x%08x, "
                            "usermode=%i\n", (int)vaddr, usermode);
                        fatal("            CS:EIP = 0x%04x:0x%016"PRIx64"\n",
                            (int) cpu->cd.x86.s[X86_S_CS], (uint64_t) cpu->pc);
                        if (!no_exceptions) {
                                cpu->cd.x86.cr[2] = vaddr;
                                x86_interrupt(cpu, 14, (writeflag? 2 : 0) +
                                    (usermode? 4 : 0));
                        }
                        return 0;
                }

                /*  Read the Page Table Entry:  */
                table_addr = pde & ~0xfff;
                res = cpu->memory_rw(cpu, cpu->mem, table_addr + 4*b, pted,
                    sizeof(pted), MEM_READ, PHYSICAL);
                if (!res) {
                        fatal("TODO: could not read pte (pt = 0x%"PRIx64")\n",
                            (uint64_t) table_addr);
                        goto fail;
                }
                pte = pted[0] + (pted[1] << 8) + (pted[2] << 16) +
                    (pted[3] << 24);
                if ((pted[0] & 0x01) && !(pted[0] & 0x20)) {
                        pted[0] |= 0x20;
                        cpu->memory_rw(cpu, cpu->mem, table_addr + 4*b, pted,
                            sizeof(pted), MEM_WRITE, PHYSICAL);
                }
                if ((pted[0] & 0x01) && writeflag == MEM_WRITE &&
                    !(pted[0] & 0x40)) {
                        pted[0] |= 0x40;
                        cpu->memory_rw(cpu, cpu->mem, table_addr + 4*b, pted,
                            sizeof(pted), MEM_WRITE, PHYSICAL);
                }
                /*  fatal("  pte: 0x%08x\n", (int)pte);  */
                if (!(pte & 0x02))
                        writable = 0;
                if (!(pte & 0x01)) {
                        fatal("TODO: pte not present: table_addr=0x%08x "
                            "vaddr=0x%08x, usermode=%i wf=%i pte=0x%08x\n",
                            (int)table_addr, (int)vaddr, usermode, writeflag,
                            (int)pte);
                        if (!no_exceptions) {
                                cpu->cd.x86.cr[2] = vaddr;
                                x86_interrupt(cpu, 14, (writeflag? 2 : 0)
                                    + (usermode? 4 : 0));
                        }
                        return 0;
                }

                (*return_addr) = (pte & ~0xfff) | (vaddr & 0xfff);
        } else
                *return_addr = vaddr;

        /*  Code:  */
        if (flags & FLAG_INSTR) {
                if (dc->descr_type == DESCR_TYPE_CODE)
                        return 1;
                fatal("TODO instr load but not code descriptor?\n");
                goto fail;
        }

        /*  We are here on non-instruction fetch.  */

        if (writeflag == MEM_WRITE && !writable) {
                if (!usermode && !(cpu->cd.x86.cr[0] & X86_CR0_WP)) {
                        /*  80386 compatiblity: allow writes to userspace,
                            if we are running in kernel mode.  */
                        writable = 1;
                } else {
                        fatal("TODO: write to nonwritable segment or page: "
                            "vaddr=0x%08x pde=0x%08x pte=0x%08x\n",
                            (int)vaddr, (int)pde, (int)pte);
                        cpu->cd.x86.cr[2] = vaddr;
                        x86_interrupt(cpu, 14, (writeflag? 2 : 0)
                            + (usermode? 4 : 0) + 1);
                        return 0;
                }
        }

        return 1 + writable;

fail:
        fatal("memory_x86 FAIL: TODO\n");
        cpu->running = 0;
        return 0;
}

1	dpavlin	14	/*
2			* Copyright (C) 2005 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	26	* $Id: memory_x86.c,v 1.3 2006/06/24 21:47:23 debug Exp $
29	dpavlin	14	*
30			* Included from cpu_x86.c.
31			*
32			*
33			* TODO: This is basically just a skeleton so far.
34			*/
35
36
37			/*
38	dpavlin	26	* translate_v2p():
39	dpavlin	14	*
40			* Return values:
41			* 0 Failure
42			* 1 Success, the page is readable only
43			* 2 Success, the page is read/write
44			*/
45			int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr,
46			uint64_t *return_addr, int flags)
47			{
48			unsigned char pded[4];
49			unsigned char pted[4];
50			uint64_t table_addr;
51			uint32_t pte=0, pde=0;
52			int a, b, res, writable, usermode = 0;
53			int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ;
54			int no_exceptions = flags & FLAG_NOEXCEPTIONS;
55			int no_segmentation = flags & NO_SEGMENTATION;
56			struct descriptor_cache *dc;
57
58			if (cpu->cd.x86.cursegment < 0 \|\| cpu->cd.x86.cursegment >= 8) {
59			fatal("TODO: Weird x86 segment nr %i\n",
60			cpu->cd.x86.cursegment);
61			cpu->running = 0;
62			return 0;
63			}
64
65			if ((vaddr >> 32) == 0xffffffff)
66			vaddr &= 0xffffffff;
67
68			dc = &cpu->cd.x86.descr_cache[cpu->cd.x86.cursegment & 7];
69
70			if (no_segmentation) {
71			/* linear address */
72			writable = 1;
73			} else {
74			if (PROTECTED_MODE && vaddr > dc->limit) {
75	dpavlin	24	fatal("TODO: vaddr=0x%"PRIx64" > limit (0x%"PRIx64")\n",
76			(uint64_t) vaddr, (uint64_t) dc->limit);
77			/* goto fail; */
78	dpavlin	14	}
79
80			/* TODO: Check the Privilege Level */
81			vaddr = (vaddr + dc->base) & 0xffffffff;
82			writable = dc->writable;
83			}
84
85			usermode = (cpu->cd.x86.s[X86_S_CS] & X86_PL_MASK) ==
86			X86_RING3;
87
88			/* Paging: */
89			if (cpu->cd.x86.cr[0] & X86_CR0_PG) {
90			/* TODO: This should be cached somewhere, in some
91			kind of simulated TLB. */
92			if (cpu->cd.x86.cr[3] & 0xfff) {
93	dpavlin	24	fatal("TODO: cr3=%016"PRIx64" (lowest bits non-zero)\n",
94			(uint64_t) cpu->cd.x86.cr[3]);
95	dpavlin	14	goto fail;
96			}
97
98			a = (vaddr >> 22) & 1023;
99			b = (vaddr >> 12) & 1023;
100			/* fatal("vaddr = 0x%08x ==> %i, %i\n", (int)vaddr, a, b); */
101
102			/* Read the Page Directory Entry: */
103			table_addr = cpu->cd.x86.cr[3] & ~0xfff;
104			if (table_addr == 0)
105			fatal("WARNING: The page directory (cr3) is at"
106			" physical address 0 (?)\n");
107			res = cpu->memory_rw(cpu, cpu->mem, table_addr + 4*a, pded,
108			sizeof(pded), MEM_READ, PHYSICAL);
109			if (!res) {
110	dpavlin	24	fatal("TODO: could not read pde (table = 0x%"PRIx64
111			")\n", (uint64_t) table_addr);
112	dpavlin	14	goto fail;
113			}
114			if ((pded[0] & 0x01) && !(pded[0] & 0x20)) {
115			pded[0] \|= 0x20;
116			cpu->memory_rw(cpu, cpu->mem, table_addr + 4*a, pded,
117			sizeof(pded), MEM_WRITE, PHYSICAL);
118			}
119			if ((pded[0] & 0x01) && writeflag == MEM_WRITE &&
120			!(pded[0] & 0x40)) {
121			pded[0] \|= 0x40;
122			cpu->memory_rw(cpu, cpu->mem, table_addr + 4*a, pded,
123			sizeof(pded), MEM_WRITE, PHYSICAL);
124			}
125			pde = pded[0] + (pded[1] << 8) + (pded[2] << 16) +
126			(pded[3] << 24);
127			/* fatal(" pde: 0x%08x\n", (int)pde); */
128			/* TODO: lowest bits of the pde */
129			if (!(pde & 0x01)) {
130			fatal("PAGE FAULT: pde not present: vaddr=0x%08x, "
131			"usermode=%i\n", (int)vaddr, usermode);
132	dpavlin	24	fatal(" CS:EIP = 0x%04x:0x%016"PRIx64"\n",
133			(int) cpu->cd.x86.s[X86_S_CS], (uint64_t) cpu->pc);
134	dpavlin	14	if (!no_exceptions) {
135			cpu->cd.x86.cr[2] = vaddr;
136			x86_interrupt(cpu, 14, (writeflag? 2 : 0) +
137			(usermode? 4 : 0));
138			}
139			return 0;
140			}
141
142			/* Read the Page Table Entry: */
143			table_addr = pde & ~0xfff;
144			res = cpu->memory_rw(cpu, cpu->mem, table_addr + 4*b, pted,
145			sizeof(pted), MEM_READ, PHYSICAL);
146			if (!res) {
147	dpavlin	24	fatal("TODO: could not read pte (pt = 0x%"PRIx64")\n",
148			(uint64_t) table_addr);
149	dpavlin	14	goto fail;
150			}
151			pte = pted[0] + (pted[1] << 8) + (pted[2] << 16) +
152			(pted[3] << 24);
153			if ((pted[0] & 0x01) && !(pted[0] & 0x20)) {
154			pted[0] \|= 0x20;
155			cpu->memory_rw(cpu, cpu->mem, table_addr + 4*b, pted,
156			sizeof(pted), MEM_WRITE, PHYSICAL);
157			}
158			if ((pted[0] & 0x01) && writeflag == MEM_WRITE &&
159			!(pted[0] & 0x40)) {
160			pted[0] \|= 0x40;
161			cpu->memory_rw(cpu, cpu->mem, table_addr + 4*b, pted,
162			sizeof(pted), MEM_WRITE, PHYSICAL);
163			}
164			/* fatal(" pte: 0x%08x\n", (int)pte); */
165			if (!(pte & 0x02))
166			writable = 0;
167			if (!(pte & 0x01)) {
168			fatal("TODO: pte not present: table_addr=0x%08x "
169			"vaddr=0x%08x, usermode=%i wf=%i pte=0x%08x\n",
170			(int)table_addr, (int)vaddr, usermode, writeflag,
171			(int)pte);
172			if (!no_exceptions) {
173			cpu->cd.x86.cr[2] = vaddr;
174			x86_interrupt(cpu, 14, (writeflag? 2 : 0)
175			+ (usermode? 4 : 0));
176			}
177			return 0;
178			}
179
180			(*return_addr) = (pte & ~0xfff) \| (vaddr & 0xfff);
181			} else
182			*return_addr = vaddr;
183
184			/* Code: */
185			if (flags & FLAG_INSTR) {
186			if (dc->descr_type == DESCR_TYPE_CODE)
187			return 1;
188			fatal("TODO instr load but not code descriptor?\n");
189			goto fail;
190			}
191
192			/* We are here on non-instruction fetch. */
193
194			if (writeflag == MEM_WRITE && !writable) {
195			if (!usermode && !(cpu->cd.x86.cr[0] & X86_CR0_WP)) {
196			/* 80386 compatiblity: allow writes to userspace,
197			if we are running in kernel mode. */
198			writable = 1;
199			} else {
200			fatal("TODO: write to nonwritable segment or page: "
201			"vaddr=0x%08x pde=0x%08x pte=0x%08x\n",
202			(int)vaddr, (int)pde, (int)pte);
203			cpu->cd.x86.cr[2] = vaddr;
204			x86_interrupt(cpu, 14, (writeflag? 2 : 0)
205			+ (usermode? 4 : 0) + 1);
206			return 0;
207			}
208			}
209
210			return 1 + writable;
211
212			fail:
213			fatal("memory_x86 FAIL: TODO\n");
214			cpu->running = 0;
215			return 0;
216			}
217